Commit 1987c79b authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/pm: align Hawaii mclk workaround with radeon 

Align the hawaii mclk workaround with radeon and windows.

Link: https://gitlab.freedesktop.org/drm/amd/-/work_items/1816


Fixes: 9f4b3541 ("drm/amd/powerplay: add CI asics support to smumgr (v3)")
Reviewed-by: default avatarTimur Kristóf <timur.kristof@gmail.com>
Reviewed-by: default avatarKent Russell <kent.russell@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 9649528b637f668c5af9f2b83ca4ad8576ae2121)
Cc: stable@vger.kernel.org
parent 2a561b36

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

+4 −4
Original line number Diff line number Diff line
@@ -1336,10 +1336,10 @@ static int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr) 
	if ((dpm_table->mclk_table.count >= 2) &&

	    ((dev_id == 0x67B0) ||  (dev_id == 0x67B1)) &&

	    (adev->pdev->revision == 0)) {

		smu_data->smc_state_table.MemoryLevel[1].MinVddci =

				smu_data->smc_state_table.MemoryLevel[0].MinVddci;

		smu_data->smc_state_table.MemoryLevel[1].MinMvdd =

				smu_data->smc_state_table.MemoryLevel[0].MinMvdd;

		smu_data->smc_state_table.MemoryLevel[1].MinVddc =

				smu_data->smc_state_table.MemoryLevel[0].MinVddc;

		smu_data->smc_state_table.MemoryLevel[1].MinVddcPhases =

				smu_data->smc_state_table.MemoryLevel[0].MinVddcPhases;

	}

	smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;

	CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel);