Commit 199888aa authored by Roman Li's avatar Roman Li Committed by Alex Deucher
Browse files

drm/amd/display: Update IPS default mode for DCN35/DCN351 



[WHY]
RCG state of IPX in idle is more stable for DCN351 and some variants of
DCN35 than IPS2.

[HOW]
Rework dm_get_default_ips_mode() to specify default per ASIC and update
DCN35/DCN351 defaults accordingly.

Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: default avatarSun peng Li <sunpeng.li@amd.com>
Signed-off-by: default avatarRoman Li <Roman.Li@amd.com>
Signed-off-by: default avatarAlex Hung <alex.hung@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 327e62f4

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+33 −17
Original line number Diff line number Diff line
@@ -1771,6 +1771,10 @@ static struct dml2_soc_bb *dm_dmub_get_vbios_bounding_box(struct amdgpu_device * 
static enum dmub_ips_disable_type dm_get_default_ips_mode(

	struct amdgpu_device *adev)

{

	enum dmub_ips_disable_type ret = DMUB_IPS_ENABLE;



	switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {

	case IP_VERSION(3, 5, 0):

		/*

		 * On DCN35 systems with Z8 enabled, it's possible for IPS2 + Z8 to

		 * cause a hard hang. A fix exists for newer PMFW.
@@ -1781,15 +1785,27 @@ static enum dmub_ips_disable_type dm_get_default_ips_mode( 
		 *

		 * When checking pmfw version, use the major and minor only.

		 */

	if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(3, 5, 0) &&

	    (adev->pm.fw_version & 0x00FFFF00) < 0x005D6300)

		return DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;



	if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 5, 0))

		return DMUB_IPS_ENABLE;



		if ((adev->pm.fw_version & 0x00FFFF00) < 0x005D6300)

			ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;

		else if (amdgpu_ip_version(adev, GC_HWIP, 0) > IP_VERSION(11, 5, 0))

			/*

			 * Other ASICs with DCN35 that have residency issues with

			 * IPS2 in idle.

			 * We want them to use IPS2 only in display off cases.

			 */

			ret =  DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;

		break;

	case IP_VERSION(3, 5, 1):

		ret =  DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;

		break;

	default:

		/* ASICs older than DCN35 do not have IPSs */

	return DMUB_IPS_DISABLE_ALL;

		if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 5, 0))

			ret = DMUB_IPS_DISABLE_ALL;

		break;

	}



	return ret;

}



static int amdgpu_dm_init(struct amdgpu_device *adev)