Commit 1998e6be authored by Alexandre Courbot's avatar Alexandre Courbot
Browse files

Documentation: nova: remove register abstraction task 



The `register!` macro has been implemented and all nova-core code
converted to use it. Remove the corresponding task in todo.rst.

Reviewed-by: default avatarEliot Courtney <ecourtney@nvidia.com>
Reviewed-by: default avatarGary Guo <gary@garyguo.net>
Acked-by: default avatarDanilo Krummrich <dakr@kernel.org>
Link: https://patch.msgid.link/20260325-b4-nova-register-v4-10-bdf172f0f6ca@nvidia.com


Signed-off-by: default avatarAlexandre Courbot <acourbot@nvidia.com>
parent 2278f97b

Documentation/gpu/nova/core/todo.rst

+0 −76
Original line number Diff line number Diff line
@@ -51,82 +51,6 @@ There also have been considerations of ToPrimitive [2]. 
| Link: https://lore.kernel.org/all/cover.1750689857.git.y.j3ms.n@gmail.com/ [1]

| Link: https://rust-for-linux.zulipchat.com/#narrow/channel/288089-General/topic/Implement.20.60FromPrimitive.60.20trait.20.2B.20derive.20macro.20for.20nova-core/with/541971854 [2]



Generic register abstraction [REGA]

-----------------------------------



Work out how register constants and structures can be automatically generated

through generalized macros.



Example:



.. code-block:: rust



	register!(BOOT0, 0x0, u32, pci::Bar<SIZE>, Fields [

	   MINOR_REVISION(3:0, RO),

	   MAJOR_REVISION(7:4, RO),

	   REVISION(7:0, RO), // Virtual register combining major and minor rev.

	])



This could expand to something like:



.. code-block:: rust



	const BOOT0_OFFSET: usize = 0x00000000;

	const BOOT0_MINOR_REVISION_SHIFT: u8 = 0;

	const BOOT0_MINOR_REVISION_MASK: u32 = 0x0000000f;

	const BOOT0_MAJOR_REVISION_SHIFT: u8 = 4;

	const BOOT0_MAJOR_REVISION_MASK: u32 = 0x000000f0;

	const BOOT0_REVISION_SHIFT: u8 = BOOT0_MINOR_REVISION_SHIFT;

	const BOOT0_REVISION_MASK: u32 = BOOT0_MINOR_REVISION_MASK | BOOT0_MAJOR_REVISION_MASK;



	struct Boot0(u32);



	impl Boot0 {

	   #[inline]

	   fn read(bar: &RevocableGuard<'_, pci::Bar<SIZE>>) -> Self {

	      Self(bar.readl(BOOT0_OFFSET))

	   }



	   #[inline]

	   fn minor_revision(&self) -> u32 {

	      (self.0 & BOOT0_MINOR_REVISION_MASK) >> BOOT0_MINOR_REVISION_SHIFT

	   }



	   #[inline]

	   fn major_revision(&self) -> u32 {

	      (self.0 & BOOT0_MAJOR_REVISION_MASK) >> BOOT0_MAJOR_REVISION_SHIFT

	   }



	   #[inline]

	   fn revision(&self) -> u32 {

	      (self.0 & BOOT0_REVISION_MASK) >> BOOT0_REVISION_SHIFT

	   }

	}



Usage:



.. code-block:: rust



	let bar = bar.try_access().ok_or(ENXIO)?;



	let boot0 = Boot0::read(&bar);

	pr_info!("Revision: {}\n", boot0.revision());



A work-in-progress implementation currently resides in

`drivers/gpu/nova-core/regs/macros.rs` and is used in nova-core. It would be

nice to improve it (possibly using proc macros) and move it to the `kernel`

crate so it can be used by other components as well.



Features desired before this happens:



* Make I/O optional I/O (for field values that are not registers),

* Support other sizes than `u32`,

* Allow visibility control for registers and individual fields,

* Use Rust slice syntax to express fields ranges.



| Complexity: Advanced

| Contact: Alexandre Courbot



Numerical operations [NUMM]

---------------------------