Commit 19b79e4f authored by Relja Vojvodic's avatar Relja Vojvodic Committed by Alex Deucher
Browse files

drm/amd/display: Rework YCbCr422 DSC policy 



- Reworked YCbCr4:2:2 Native/Simple policy decision making with DSC
enabled based on DSC caps and stream signal type

Reviewed-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Signed-off-by: default avatarRelja Vojvodic <Relja.Vojvodic@amd.com>
Signed-off-by: default avatarChuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3967ab83

drivers/gpu/drm/amd/display/dc/dc.h

+1 −1
Original line number Diff line number Diff line
@@ -563,6 +563,7 @@ struct dc_config { 
	bool frame_update_cmd_version2;

	struct spl_sharpness_range dcn_sharpness_range;

	struct spl_sharpness_range dcn_override_sharpness_range;

	bool no_native422_support;

};



enum visual_confirm {
@@ -987,7 +988,6 @@ struct link_service; 
 * causing an issue or not.

 */

struct dc_debug_options {

	bool native422_support;

	bool disable_dsc;

	enum visual_confirm visual_confirm;

	int visual_confirm_rect_height;

drivers/gpu/drm/amd/display/dc/dc_dsc.h

+1 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ struct dc_dsc_policy { 
	uint32_t max_target_bpp;

	uint32_t min_target_bpp;

	bool enable_dsc_when_not_needed;

	bool ycbcr422_simple;

};



struct dc_dsc_config_options {

drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c

+3 −3
Original line number Diff line number Diff line
@@ -1174,12 +1174,12 @@ static unsigned int map_plane_to_dml_display_cfg(const struct dml2_context *dml2 
		const struct dc_state *context, const struct dml_display_cfg_st *dml_dispcfg, unsigned int stream_id, int plane_index)

{

	unsigned int plane_id;

	int i = 0;

	int location = -1;

	unsigned int i = 0;

	unsigned int location = UINT_MAX;



	if (!get_plane_id(context->bw_ctx.dml2, context, plane, stream_id, plane_index, &plane_id)) {

		ASSERT(false);

		return -1;

		return UINT_MAX;

	}



	for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

+6 −7
Original line number Diff line number Diff line
@@ -680,9 +680,6 @@ static void get_dsc_enc_caps( 
	} else {

		build_dsc_enc_caps(dsc, dsc_enc_caps);

	}



	if (dsc->ctx->dc->debug.native422_support)

		dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1;

}



/* Returns 'false' if no intersection was found for at least one capability.
@@ -1100,13 +1097,14 @@ static bool setup_dsc_config( 
		branch_max_throughput_mps = dsc_sink_caps->branch_overall_throughput_0_mps;

		break;

	case PIXEL_ENCODING_YCBCR422:

		is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_NATIVE_422;

		sink_per_slice_throughput_mps = dsc_sink_caps->throughput_mode_1_mps;

		branch_max_throughput_mps = dsc_sink_caps->branch_overall_throughput_1_mps;

		if (!is_dsc_possible) {

		if (policy.ycbcr422_simple) {

			is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_SIMPLE_422;

			dsc_cfg->ycbcr422_simple = is_dsc_possible;

			sink_per_slice_throughput_mps = dsc_sink_caps->throughput_mode_0_mps;

		} else {

			is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_NATIVE_422;

			sink_per_slice_throughput_mps = dsc_sink_caps->throughput_mode_1_mps;

			branch_max_throughput_mps = dsc_sink_caps->branch_overall_throughput_1_mps;

		}

		break;

	case PIXEL_ENCODING_YCBCR420:
@@ -1406,6 +1404,7 @@ void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, 
		policy->min_target_bpp = 8;

		/* DP specs limits to 3 x bpc */

		policy->max_target_bpp = 3 * bpc;

		policy->ycbcr422_simple = true;

		break;

	case PIXEL_ENCODING_YCBCR420:

		/* DP specs limits to 6 */

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

+1 −1
Original line number Diff line number Diff line
@@ -100,7 +100,7 @@ void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz) 
	dsc_enc_caps->color_formats.bits.RGB = 1;

	dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;

	dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;

	dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0;

	dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1;

	dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;



	dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;