Commit 19cd8c8b authored by Yann Dirson's avatar Yann Dirson Committed by Alex Deucher
Browse files

Documentation/gpu: include description of some of the GC microcontrollers 

This is Alex' description from the "Looking for clarifications around gfx/kcq/kiq"
thread, edited to fit as ReST.

Original text: https://www.spinics.net/lists/amd-gfx/msg71383.html



Originally-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarYann Dirson <ydirson@free.fr>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Reviewed-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d59f1774

Documentation/gpu/amdgpu/driver-core.rst

+35 −0
Original line number Diff line number Diff line
@@ -76,6 +76,28 @@ VCN (Video Core Next) 
    decode.  It's exposed to userspace for user mode drivers (VA-API,

    OpenMAX, etc.)



Graphics and Compute Microcontrollers

-------------------------------------



CP (Command Processor)

    The name for the hardware block that encompasses the front end of the

    GFX/Compute pipeline.  Consists mainly of a bunch of microcontrollers

    (PFP, ME, CE, MEC).  The firmware that runs on these microcontrollers

    provides the driver interface to interact with the GFX/Compute engine.



    MEC (MicroEngine Compute)

        This is the microcontroller that controls the compute queues on the

        GFX/compute engine.



    MES (MicroEngine Scheduler)

        This is a new engine for managing queues.  This is currently unused.



RLC (RunList Controller)

    This is another microcontroller in the GFX/Compute engine.  It handles

    power management related functionality within the GFX/Compute engine.

    The name is a vestige of old hardware where it was originally added

    and doesn't really have much relation to what the engine does now.



Driver Structure

================
@@ -83,6 +105,19 @@ In general, the driver has a list of all of the IPs on a particular 
SoC and for things like init/fini/suspend/resume, more or less just

walks the list and handles each IP.



Some useful constructs:



KIQ (Kernel Interface Queue)

    This is a control queue used by the kernel driver to manage other gfx

    and compute queues on the GFX/compute engine.  You can use it to

    map/unmap additional queues, etc.



IB (Indirect Buffer)

    A command buffer for a particular engine.  Rather than writing

    commands directly to the queue, you can write the commands into a

    piece of memory and then put a pointer to the memory into the queue.

    The hardware will then follow the pointer and execute the commands in

    the memory, then returning to the rest of the commands in the ring.



.. _amdgpu_memory_domains: