Commit 1a1e6865 authored by Shivaprasad G Bhat's avatar Shivaprasad G Bhat Committed by Michael Ellerman
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KVM: PPC: Book3S HV: Add one-reg interface for DEXCR register



The patch adds a one-reg register identifier which can be used to
read and set the DEXCR for the guest during enter/exit with
KVM_REG_PPC_DEXCR. The specific SPR KVM API documentation
too updated.

Signed-off-by: default avatarShivaprasad G Bhat <sbhat@linux.ibm.com>
Reviewed-by: default avatarNicholas Piggin <npiggin@gmail.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://msgid.link/171759279613.1480.12873911783530175699.stgit@linux.ibm.com
parent 009f6f42
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+1 −0
Original line number Diff line number Diff line
@@ -2441,6 +2441,7 @@ registers, find a list below:
  PPC     KVM_REG_PPC_PTCR                64
  PPC     KVM_REG_PPC_DAWR1               64
  PPC     KVM_REG_PPC_DAWRX1              64
  PPC     KVM_REG_PPC_DEXCR               64
  PPC     KVM_REG_PPC_TM_GPR0             64
  ...
  PPC     KVM_REG_PPC_TM_GPR31            64
+1 −0
Original line number Diff line number Diff line
@@ -599,6 +599,7 @@ struct kvm_vcpu_arch {
	ulong dawrx0;
	ulong dawr1;
	ulong dawrx1;
	ulong dexcr;
	ulong ciabr;
	ulong cfar;
	ulong ppr;
+1 −0
Original line number Diff line number Diff line
@@ -645,6 +645,7 @@ struct kvm_ppc_cpu_char {
#define KVM_REG_PPC_SIER3	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc3)
#define KVM_REG_PPC_DAWR1	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc4)
#define KVM_REG_PPC_DAWRX1	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc5)
#define KVM_REG_PPC_DEXCR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc6)

/* Transactional Memory checkpointed state:
 * This is all GPRs, all VSX regs and a subset of SPRs
+6 −0
Original line number Diff line number Diff line
@@ -2349,6 +2349,9 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
	case KVM_REG_PPC_DAWRX1:
		*val = get_reg_val(id, kvmppc_get_dawrx1_hv(vcpu));
		break;
	case KVM_REG_PPC_DEXCR:
		*val = get_reg_val(id, kvmppc_get_dexcr_hv(vcpu));
		break;
	case KVM_REG_PPC_CIABR:
		*val = get_reg_val(id, kvmppc_get_ciabr_hv(vcpu));
		break;
@@ -2592,6 +2595,9 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
	case KVM_REG_PPC_DAWRX1:
		kvmppc_set_dawrx1_hv(vcpu, set_reg_val(id, *val) & ~DAWRX_HYP);
		break;
	case KVM_REG_PPC_DEXCR:
		kvmppc_set_dexcr_hv(vcpu, set_reg_val(id, *val));
		break;
	case KVM_REG_PPC_CIABR:
		kvmppc_set_ciabr_hv(vcpu, set_reg_val(id, *val));
		/* Don't allow setting breakpoints in hypervisor code */
+1 −0
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@@ -116,6 +116,7 @@ KVMPPC_BOOK3S_HV_VCPU_ACCESSOR(dawr0, 64, KVMPPC_GSID_DAWR0)
KVMPPC_BOOK3S_HV_VCPU_ACCESSOR(dawr1, 64, KVMPPC_GSID_DAWR1)
KVMPPC_BOOK3S_HV_VCPU_ACCESSOR(dawrx0, 64, KVMPPC_GSID_DAWRX0)
KVMPPC_BOOK3S_HV_VCPU_ACCESSOR(dawrx1, 64, KVMPPC_GSID_DAWRX1)
KVMPPC_BOOK3S_HV_VCPU_ACCESSOR(dexcr, 64, KVMPPC_GSID_DEXCR)
KVMPPC_BOOK3S_HV_VCPU_ACCESSOR(ciabr, 64, KVMPPC_GSID_CIABR)
KVMPPC_BOOK3S_HV_VCPU_ACCESSOR(wort, 64, KVMPPC_GSID_WORT)
KVMPPC_BOOK3S_HV_VCPU_ACCESSOR(ppr, 64, KVMPPC_GSID_PPR)