Commit 1a28651c authored by Matt Roper's avatar Matt Roper
Browse files

drm/xe: Move 'has_flatccs' flag back to platform descriptor 



FlatCCS presence/absence is a flag that should be tracked at the
platform level rather than the IP level.  FlatCCS affects the
device-wide memory initialization and reservations so its effects are
not confined to a single IP block or GT.  This is also a trait that
should be tied to the platform even if the graphics IP itself is not
present (e.g., if we disable the primary GT via configfs).

Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20251013200944.2499947-31-matthew.d.roper@intel.com


Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
parent 76b7aedd

drivers/gpu/drm/xe/xe_pci.c

+6 −6
Original line number Diff line number Diff line
@@ -63,8 +63,6 @@ static const struct xe_graphics_desc graphics_xehpg = { 
		BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),



	XE_HP_FEATURES,



	.has_flat_ccs = 1,

};



static const struct xe_graphics_desc graphics_xehpc = {
@@ -95,7 +93,6 @@ static const struct xe_graphics_desc graphics_xelpg = { 
#define XE2_GFX_FEATURES \

	.has_asid = 1, \

	.has_atomic_enable_pte_bit = 1, \

	.has_flat_ccs = 1, \

	.has_range_tlb_inval = 1, \

	.has_usm = 1, \

	.has_64bit_timestamp = 1, \
@@ -259,6 +256,7 @@ static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 }; 
#define DG2_FEATURES \

	DGFX_FEATURES, \

	PLATFORM(DG2), \

	.has_flat_ccs = 1, \

	.has_gsc_nvm = 1, \

	.has_heci_gscfi = 1, \

	.subplatforms = (const struct xe_subplatform_desc[]) { \
@@ -329,6 +327,7 @@ static const struct xe_device_desc lnl_desc = { 
	PLATFORM(LUNARLAKE),

	.dma_mask_size = 46,

	.has_display = true,

	.has_flat_ccs = 1,

	.has_pxp = true,

	.max_gt_per_tile = 2,

	.needs_scratch = true,
@@ -342,6 +341,7 @@ static const struct xe_device_desc bmg_desc = { 
	.dma_mask_size = 46,

	.has_display = true,

	.has_fan_control = true,

	.has_flat_ccs = 1,

	.has_mbx_power_limits = true,

	.has_gsc_nvm = 1,

	.has_heci_cscfi = 1,
@@ -357,6 +357,7 @@ static const struct xe_device_desc ptl_desc = { 
	PLATFORM(PANTHERLAKE),

	.dma_mask_size = 46,

	.has_display = true,

	.has_flat_ccs = 1,

	.has_sriov = true,

	.max_gt_per_tile = 2,

	.needs_scratch = true,
@@ -604,6 +605,8 @@ static int xe_info_init_early(struct xe_device *xe, 


	xe->info.is_dgfx = desc->is_dgfx;

	xe->info.has_fan_control = desc->has_fan_control;

	/* runtime fusing may force flat_ccs to disabled later */

	xe->info.has_flat_ccs = desc->has_flat_ccs;

	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;

	xe->info.has_gsc_nvm = desc->has_gsc_nvm;

	xe->info.has_heci_gscfi = desc->has_heci_gscfi;
@@ -736,9 +739,6 @@ static int xe_info_init(struct xe_device *xe, 
	if (xe->info.platform != XE_PVC)

		xe->info.has_device_atomics_on_smem = 1;



	/* Runtime detection may change this later */

	xe->info.has_flat_ccs = graphics_desc->has_flat_ccs;



	xe->info.has_range_tlb_inval = graphics_desc->has_range_tlb_inval;

	xe->info.has_usm = graphics_desc->has_usm;

	xe->info.has_64bit_timestamp = graphics_desc->has_64bit_timestamp;

drivers/gpu/drm/xe/xe_pci_types.h

+1 −1
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ struct xe_device_desc { 


	u8 has_display:1;

	u8 has_fan_control:1;

	u8 has_flat_ccs:1;

	u8 has_gsc_nvm:1;

	u8 has_heci_gscfi:1;

	u8 has_heci_cscfi:1;
@@ -59,7 +60,6 @@ struct xe_graphics_desc { 


	u8 has_asid:1;

	u8 has_atomic_enable_pte_bit:1;

	u8 has_flat_ccs:1;

	u8 has_indirect_ring_state:1;

	u8 has_range_tlb_inval:1;

	u8 has_usm:1;