Commit 1a47520b authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm8250: switch USB+DP QMP PHY to new style of bindings 



Change the USB QMP PHY to use newer style of QMP PHY bindings (single
resource region, no per-PHY subnodes).

Reviewed-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230711120916.4165894-11-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 0459c56e

arch/arm64/boot/dts/qcom/sm8250.dtsi

+14 −35
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include <dt-bindings/interconnect/qcom,osm-l3.h>

#include <dt-bindings/interconnect/qcom,sm8250.h>

#include <dt-bindings/mailbox/qcom-ipcc.h>

#include <dt-bindings/phy/phy-qcom-qmp.h>

#include <dt-bindings/power/qcom-rpmpd.h>

#include <dt-bindings/power/qcom,rpmhpd.h>

#include <dt-bindings/soc/qcom,apr.h>
@@ -3580,48 +3581,26 @@ usb_2_hsphy: phy@88e4000 { 
			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;

		};



		usb_1_qmpphy: phy@88e9000 {

		usb_1_qmpphy: phy@88e8000 {

			compatible = "qcom,sm8250-qmp-usb3-dp-phy";

			reg = <0 0x088e9000 0 0x200>,

			      <0 0x088e8000 0 0x40>,

			      <0 0x088ea000 0 0x200>;

			reg = <0 0x088e8000 0 0x3000>;

			status = "disabled";

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;



			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,

				 <&rpmhcc RPMH_CXO_CLK>,

				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;

			clock-names = "aux", "ref_clk_src", "com_aux";

				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,

				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;

			clock-names = "aux",

				      "ref",

				      "com_aux",

				      "usb3_pipe";



			resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,

				 <&gcc GCC_USB3_PHY_PRIM_BCR>;

			reset-names = "phy", "common";



			usb_1_ssphy: usb3-phy@88e9200 {

				reg = <0 0x088e9200 0 0x200>,

				      <0 0x088e9400 0 0x200>,

				      <0 0x088e9c00 0 0x400>,

				      <0 0x088e9600 0 0x200>,

				      <0 0x088e9800 0 0x200>,

				      <0 0x088e9a00 0 0x100>;

				#clock-cells = <0>;

				#phy-cells = <0>;

				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;

				clock-names = "pipe0";

				clock-output-names = "usb3_phy_pipe_clk_src";

			};



			dp_phy: dp-phy@88ea200 {

				reg = <0 0x088ea200 0 0x200>,

				      <0 0x088ea400 0 0x200>,

				      <0 0x088eaa00 0 0x200>,

				      <0 0x088ea600 0 0x200>,

				      <0 0x088ea800 0 0x200>;

				#phy-cells = <0>;

			#clock-cells = <1>;

			};

			#phy-cells = <1>;

		};



		usb_2_qmpphy: phy@88eb000 {
@@ -3892,7 +3871,7 @@ usb_1_dwc3: usb@a600000 { 
				iommus = <&apps_smmu 0x0 0x0>;

				snps,dis_u2_susphy_quirk;

				snps,dis_enblslpm_quirk;

				phys = <&usb_1_hsphy>, <&usb_1_ssphy>;

				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;

				phy-names = "usb2-phy", "usb3-phy";

			};

		};
@@ -4586,8 +4565,8 @@ dispcc: clock-controller@af00000 { 
				 <&mdss_dsi0_phy 1>,

				 <&mdss_dsi1_phy 0>,

				 <&mdss_dsi1_phy 1>,

				 <&dp_phy 0>,

				 <&dp_phy 1>;

				 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,

				 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;

			clock-names = "bi_tcxo",

				      "dsi0_phy_pll_out_byteclk",

				      "dsi0_phy_pll_out_dsiclk",