Commit 1a736d98 authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

Revert "powerpc/8xx: Always pin kernel text TLB" 



This reverts commit bccc5898.

When STRICT_KERNEL_RWX is selected, EXEC memory must stop where
RW memory start. When pinning iTLBs it means an 8M alignment for
RW data start. That may be acceptable on boards with a lot of
memory but one of my supported boards only has 32 Mbytes and this
forced alignment leads to a waste of almost 4 Mbytes with is more
than 10% of the total memory.

So revert commit bccc5898 ("powerpc/8xx: Always pin kernel text
TLB") but don't restore previous behaviour in ITLB miss handler
as now kernel PGD entries are copied into each process PGDIR.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://msgid.link/01b6780b860c8043b51a1ba9d83acfc6f2dde910.1724173828.git.christophe.leroy@csgroup.eu
parent 985db026

arch/powerpc/kernel/head_8xx.S

+8 −0
Original line number Diff line number Diff line
@@ -587,6 +587,10 @@ start_here: 
	lis	r0, (MD_TWAM | MD_RSV4I)@h

	mtspr	SPRN_MD_CTR, r0

#endif

#ifndef CONFIG_PIN_TLB_TEXT

	li	r0, 0

	mtspr	SPRN_MI_CTR, r0

#endif

#if !defined(CONFIG_PIN_TLB_DATA) && !defined(CONFIG_PIN_TLB_IMMR)

	lis	r0, MD_TWAM@h

	mtspr	SPRN_MD_CTR, r0
@@ -683,6 +687,7 @@ SYM_FUNC_START_LOCAL(initial_mmu) 
	blr

SYM_FUNC_END(initial_mmu)



#ifdef CONFIG_PIN_TLB

_GLOBAL(mmu_pin_tlb)

	lis	r9, (1f - PAGE_OFFSET)@h

	ori	r9, r9, (1f - PAGE_OFFSET)@l
@@ -704,6 +709,7 @@ _GLOBAL(mmu_pin_tlb) 
	mtspr	SPRN_MD_CTR, r6

	tlbia



#ifdef CONFIG_PIN_TLB_TEXT

	LOAD_REG_IMMEDIATE(r5, 28 << 8)

	LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET)

	LOAD_REG_IMMEDIATE(r7, MI_SVALID | MI_PS8MEG | _PMD_ACCESSED)
@@ -724,6 +730,7 @@ _GLOBAL(mmu_pin_tlb) 
	bdnzt	lt, 2b

	lis	r0, MI_RSV4I@h

	mtspr	SPRN_MI_CTR, r0

#endif



	LOAD_REG_IMMEDIATE(r5, 28 << 8 | MD_TWAM)

#ifdef CONFIG_PIN_TLB_DATA
@@ -783,3 +790,4 @@ _GLOBAL(mmu_pin_tlb) 
	mtspr	SPRN_SRR1, r10

	mtspr	SPRN_SRR0, r11

	rfi

#endif

arch/powerpc/mm/nohash/8xx.c

+2 −1
Original line number Diff line number Diff line
@@ -177,6 +177,7 @@ int mmu_mark_initmem_nx(void) 
	if (!debug_pagealloc_enabled_or_kfence())

		err = mmu_mapin_ram_chunk(boundary, einittext8, PAGE_KERNEL, false);



	if (IS_ENABLED(CONFIG_PIN_TLB_TEXT))

		mmu_pin_tlb(block_mapped_ram, false);



	return err;

arch/powerpc/platforms/8xx/Kconfig

+7 −0
Original line number Diff line number Diff line
@@ -195,6 +195,13 @@ config PIN_TLB_IMMR 
	  CONFIG_PIN_TLB_DATA is also selected, it will reduce

	  CONFIG_PIN_TLB_DATA to 24 Mbytes.



config PIN_TLB_TEXT

	bool "Pinned TLB for TEXT"

	depends on PIN_TLB

	default y

	help

	  This pins kernel text with 8M pages.



endmenu



endmenu