Commit 1a9544b8 authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno Committed by Bjorn Andersson
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arm64: dts: qcom: msm8998: Add disabled support for LPASS iommu for Q6 



Add support for the LPASS (Q6) SMMU and keep it disabled as this is
used only when the audio DSP is present and used, which is not
mandatory to have.

It is expected for board-specific device-trees to enable this node
if supported.

Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: default avatarMarc Gonzalez <mgonzalez@freebox.fr>
Link: https://lore.kernel.org/r/20240814-lpass-v1-3-a5bb8f9dfa8b@freebox.fr


[bjorn: s/iface/bus in clock-names, to match binding]
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 562a2a89

arch/arm64/boot/dts/qcom/msm8998.dtsi

+27 −0
Original line number Diff line number Diff line
@@ -1586,6 +1586,33 @@ gpucc: clock-controller@5065000 { 
				      "gpll0";

		};



		lpass_q6_smmu: iommu@5100000 {

			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";

			reg = <0x05100000 0x40000>;

			clocks = <&gcc HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;

			clock-names = "bus";



			#global-interrupts = <0>;

			#iommu-cells = <1>;

			interrupts =

				<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;



			power-domains = <&gcc LPASS_ADSP_GDSC>;

			status = "disabled";

		};



		remoteproc_slpi: remoteproc@5800000 {

			compatible = "qcom,msm8998-slpi-pas";

			reg = <0x05800000 0x4040>;