Commit 1ad66039 authored by John Madieu's avatar John Madieu Committed by Geert Uytterhoeven
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arm64: dts: renesas: r9a09g047: Add TSU node



Add TSU node along with thermal zones and keep it enabled in the SoC DTSI.

Signed-off-by: default avatarJohn Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250917170202.197929-4-john.madieu.xa@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 45447550
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+48 −0
Original line number Diff line number Diff line
@@ -64,6 +64,7 @@ cpu0: cpu@0 {
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
			clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>;
			#cooling-cells = <2>;
			operating-points-v2 = <&cluster0_opp>;
		};

@@ -74,6 +75,7 @@ cpu1: cpu@100 {
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
			clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>;
			#cooling-cells = <2>;
			operating-points-v2 = <&cluster0_opp>;
		};

@@ -84,6 +86,7 @@ cpu2: cpu@200 {
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
			clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>;
			#cooling-cells = <2>;
			operating-points-v2 = <&cluster0_opp>;
		};

@@ -94,6 +97,7 @@ cpu3: cpu@300 {
			next-level-cache = <&L3_CA55>;
			enable-method = "psci";
			clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>;
			#cooling-cells = <2>;
			operating-points-v2 = <&cluster0_opp>;
		};

@@ -617,6 +621,19 @@ wdt3: watchdog@13000400 {
			status = "disabled";
		};

		tsu: thermal@14002000 {
			compatible = "renesas,r9a09g047-tsu";
			reg = <0 0x14002000 0 0x1000>;
			interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "adi", "adcmpi";
			clocks = <&cpg CPG_MOD 0x10a>;
			resets = <&cpg 0xf8>;
			power-domains = <&cpg>;
			#thermal-sensor-cells = <0>;
			renesas,tsu-trim = <&sys 0x330>;
		};

		i2c0: i2c@14400400 {
			compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
			reg = <0 0x14400400 0 0x400>;
@@ -1173,6 +1190,37 @@ stmmac_axi_setup: stmmac-axi-config {
		snps,blen = <16 8 4 0 0 0 0>;
	};

	thermal-zones {
		cpu-thermal {
			polling-delay = <1000>;
			polling-delay-passive = <250>;
			thermal-sensors = <&tsu>;

			cooling-maps {
				map0 {
					trip = <&target>;
					cooling-device = <&cpu0 0 3>, <&cpu1 0 3>,
							 <&cpu2 0 3>, <&cpu3 0 3>;
					contribution = <1024>;
				};
			};

			trips {
				target: trip-point {
					temperature = <95000>;
					hysteresis = <1000>;
					type = "passive";
				};

				sensor_crit: sensor-crit {
					temperature = <120000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,