Commit 1aee577b authored by Abel Vesa's avatar Abel Vesa Committed by Dmitry Baryshkov
Browse files

dt-bindings: display: msm: Document the Glymur Mobile Display SubSystem 



The MDSS/MDP display subsystem found on Glymur platform is 2 minor version
increase compared to SM8750, which makes it incompatible with all previous
platforms. So document it.

Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/683714/
Link: https://lore.kernel.org/r/20251027-glymur-display-v3-1-aa13055818ac@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
parent d9792823

Documentation/devicetree/bindings/display/msm/qcom,glymur-mdss.yaml

0 → 100644
+264 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/msm/qcom,glymur-mdss.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Glymur Display MDSS



maintainers:

  - Abel Vesa <abel.vesa@linaro.org>



description:

  Glymur MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like

  DPU display controller, DP interfaces, etc.



$ref: /schemas/display/msm/mdss-common.yaml#



properties:

  compatible:

    const: qcom,glymur-mdss



  clocks:

    items:

      - description: Display AHB

      - description: Display hf AXI

      - description: Display core



  iommus:

    maxItems: 1



  interconnects:

    items:

      - description: Interconnect path from mdp0 port to the data bus

      - description: Interconnect path from CPU to the reg bus



  interconnect-names:

    items:

      - const: mdp0-mem

      - const: cpu-cfg



patternProperties:

  "^display-controller@[0-9a-f]+$":

    type: object

    additionalProperties: true

    properties:

      compatible:

        const: qcom,glymur-dpu



  "^displayport-controller@[0-9a-f]+$":

    type: object

    additionalProperties: true

    properties:

      compatible:

        const: qcom,glymur-dp



  "^phy@[0-9a-f]+$":

    type: object

    additionalProperties: true

    properties:

      compatible:

        const: qcom,glymur-dp-phy



required:

  - compatible



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/interconnect/qcom,icc.h>

    #include <dt-bindings/interconnect/qcom,glymur-rpmh.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/phy/phy-qcom-qmp.h>

    #include <dt-bindings/power/qcom,rpmhpd.h>



    display-subsystem@ae00000 {

            compatible = "qcom,glymur-mdss";

            reg = <0x0ae00000 0x1000>;

            reg-names = "mdss";



            interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;



            clocks = <&dispcc_ahb_clk>,

                     <&gcc_disp_hf_axi_clk>,

                     <&dispcc_mdp_clk>;

            clock-names = "bus", "nrt_bus", "core";



            interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS

                             &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,

                            <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY

                             &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;

            interconnect-names = "mdp0-mem",

                                 "cpu-cfg";



            resets = <&disp_cc_mdss_core_bcr>;



            power-domains = <&mdss_gdsc>;



            iommus = <&apps_smmu 0x1c00 0x2>;



            interrupt-controller;

            #interrupt-cells = <1>;



            #address-cells = <1>;

            #size-cells = <1>;

            ranges;



            display-controller@ae01000 {

                compatible = "qcom,glymur-dpu";

                reg = <0x0ae01000 0x8f000>,

                      <0x0aeb0000 0x2008>;

                reg-names = "mdp", "vbif";



                clocks = <&gcc_axi_clk>,

                         <&dispcc_ahb_clk>,

                         <&dispcc_mdp_lut_clk>,

                         <&dispcc_mdp_clk>,

                         <&dispcc_mdp_vsync_clk>;

                clock-names = "nrt_bus",

                              "iface",

                              "lut",

                              "core",

                              "vsync";



                assigned-clocks = <&dispcc_mdp_vsync_clk>;

                assigned-clock-rates = <19200000>;



                operating-points-v2 = <&mdp_opp_table>;

                power-domains = <&rpmhpd RPMHPD_MMCX>;



                interrupt-parent = <&mdss>;

                interrupts = <0>;



                ports {

                    #address-cells = <1>;

                    #size-cells = <0>;



                    port@0 {

                        reg = <0>;

                        dpu_intf1_out: endpoint {

                            remote-endpoint = <&dsi0_in>;

                        };

                    };



                    port@1 {

                        reg = <1>;

                        dpu_intf2_out: endpoint {

                            remote-endpoint = <&dsi1_in>;

                        };

                    };

                };



                mdp_opp_table: opp-table {

                    compatible = "operating-points-v2";



                    opp-200000000 {

                        opp-hz = /bits/ 64 <200000000>;

                        required-opps = <&rpmhpd_opp_low_svs>;

                    };



                    opp-325000000 {

                        opp-hz = /bits/ 64 <325000000>;

                        required-opps = <&rpmhpd_opp_svs>;

                    };



                    opp-375000000 {

                        opp-hz = /bits/ 64 <375000000>;

                        required-opps = <&rpmhpd_opp_svs_l1>;

                    };



                    opp-514000000 {

                        opp-hz = /bits/ 64 <514000000>;

                        required-opps = <&rpmhpd_opp_nom>;

                    };

                };

            };



            displayport-controller@ae90000 {

                compatible = "qcom,glymur-dp";

                reg = <0xae90000 0x200>,

                      <0xae90200 0x200>,

                      <0xae90400 0x600>,

                      <0xae91000 0x400>,

                      <0xae91400 0x400>;



                interrupt-parent = <&mdss>;

                interrupts = <12>;



                clocks = <&dispcc_mdss_ahb_clk>,

                         <&dispcc_dptx0_aux_clk>,

                         <&dispcc_dptx0_link_clk>,

                         <&dispcc_dptx0_link_intf_clk>,

                         <&dispcc_dptx0_pixel0_clk>,

                         <&dispcc_dptx0_pixel1_clk>;

                clock-names = "core_iface",

                              "core_aux",

                              "ctrl_link",

                              "ctrl_link_iface",

                              "stream_pixel",

                              "stream_1_pixel";



                assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,

                                  <&dispcc_mdss_dptx0_pixel0_clk_src>,

                                  <&dispcc_mdss_dptx0_pixel1_clk_src>;

                assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,

                                         <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,

                                         <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;



                operating-points-v2 = <&mdss_dp0_opp_table>;



                power-domains = <&rpmhpd RPMHPD_MMCX>;



                phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>;

                phy-names = "dp";



                #sound-dai-cells = <0>;



                ports {

                    #address-cells = <1>;

                    #size-cells = <0>;



                    port@0 {

                        reg = <0>;



                        mdss_dp0_in: endpoint {

                          remote-endpoint = <&mdss_intf0_out>;

                        };

                    };



                    port@1 {

                        reg = <1>;



                        mdss_dp0_out: endpoint {

                        };

                    };

                };



                mdss_dp0_opp_table: opp-table {

                    compatible = "operating-points-v2";



                    opp-160000000 {

                        opp-hz = /bits/ 64 <160000000>;

                        required-opps = <&rpmhpd_opp_low_svs>;

                    };



                    opp-270000000 {

                        opp-hz = /bits/ 64 <270000000>;

                        required-opps = <&rpmhpd_opp_svs>;

                    };



                    opp-540000000 {

                        opp-hz = /bits/ 64 <540000000>;

                        required-opps = <&rpmhpd_opp_svs_l1>;

                    };



                    opp-810000000 {

                        opp-hz = /bits/ 64 <810000000>;

                        required-opps = <&rpmhpd_opp_nom>;

                    };

                };

            };

        };

...