Commit 1b2231de authored by Stanley.Yang's avatar Stanley.Yang Committed by Alex Deucher
Browse files

drm/amdgpu: Register aqua vanjaram jpeg poison irq 



Register aqua vanjaram jpeg poison irq, add jpeg poison handle.

Signed-off-by: default avatarStanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4c4a8914

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

+76 −0
Original line number Diff line number Diff line
@@ -149,6 +149,18 @@ static int jpeg_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) 
			return r;

	}



	/* JPEG DJPEG POISON EVENT */

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,

			VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq);

	if (r)

		return r;



	/* JPEG EJPEG POISON EVENT */

	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,

			VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq);

	if (r)

		return r;



	r = amdgpu_jpeg_sw_init(adev);

	if (r)

		return r;
@@ -434,6 +446,9 @@ static int jpeg_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block) 
			ret = jpeg_v4_0_3_set_powergating_state(ip_block, AMD_PG_STATE_GATE);

	}



	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG))

		amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0);



	return ret;

}
@@ -1041,6 +1056,14 @@ static int jpeg_v4_0_3_set_interrupt_state(struct amdgpu_device *adev, 
	return 0;

}



static int jpeg_v4_0_3_set_ras_interrupt_state(struct amdgpu_device *adev,

					struct amdgpu_irq_src *source,

					unsigned int type,

					enum amdgpu_interrupt_state state)

{

	return 0;

}



static int jpeg_v4_0_3_process_interrupt(struct amdgpu_device *adev,

				      struct amdgpu_irq_src *source,

				      struct amdgpu_iv_entry *entry)
@@ -1200,6 +1223,11 @@ static const struct amdgpu_irq_src_funcs jpeg_v4_0_3_irq_funcs = { 
	.process = jpeg_v4_0_3_process_interrupt,

};



static const struct amdgpu_irq_src_funcs jpeg_v4_0_3_ras_irq_funcs = {

	.set = jpeg_v4_0_3_set_ras_interrupt_state,

	.process = amdgpu_jpeg_process_poison_irq,

};



static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev)

{

	int i;
@@ -1208,6 +1236,9 @@ static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) 
		adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings;

	}

	adev->jpeg.inst->irq.funcs = &jpeg_v4_0_3_irq_funcs;



	adev->jpeg.inst->ras_poison_irq.num_types = 1;

	adev->jpeg.inst->ras_poison_irq.funcs = &jpeg_v4_0_3_ras_irq_funcs;

}



const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block = {
@@ -1304,9 +1335,47 @@ static void jpeg_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev) 
		jpeg_v4_0_3_inst_reset_ras_error_count(adev, i);

}



static uint32_t jpeg_v4_0_3_query_poison_by_instance(struct amdgpu_device *adev,

		uint32_t instance, uint32_t sub_block)

{

	uint32_t poison_stat = 0, reg_value = 0;



	switch (sub_block) {

	case AMDGPU_JPEG_V4_0_3_JPEG0:

		reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS);

		poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF);

		break;

	case AMDGPU_JPEG_V4_0_3_JPEG1:

		reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS);

		poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF);

		break;

	default:

		break;

	}



	if (poison_stat)

		dev_info(adev->dev, "Poison detected in JPEG%d sub_block%d\n",

			instance, sub_block);



	return poison_stat;

}



static bool jpeg_v4_0_3_query_ras_poison_status(struct amdgpu_device *adev)

{

	uint32_t inst = 0, sub = 0, poison_stat = 0;



	for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++)

		for (sub = 0; sub < AMDGPU_JPEG_V4_0_3_MAX_SUB_BLOCK; sub++)

			poison_stat +=

			jpeg_v4_0_3_query_poison_by_instance(adev, inst, sub);



	return !!poison_stat;

}



static const struct amdgpu_ras_block_hw_ops jpeg_v4_0_3_ras_hw_ops = {

	.query_ras_error_count = jpeg_v4_0_3_query_ras_error_count,

	.reset_ras_error_count = jpeg_v4_0_3_reset_ras_error_count,

	.query_poison_status = jpeg_v4_0_3_query_ras_poison_status,

};



static int jpeg_v4_0_3_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,
@@ -1383,6 +1452,13 @@ static int jpeg_v4_0_3_ras_late_init(struct amdgpu_device *adev, struct ras_comm 
	if (r)

		return r;



	if (amdgpu_ras_is_supported(adev, ras_block->block) &&

		adev->jpeg.inst->ras_poison_irq.funcs) {

		r = amdgpu_irq_get(adev, &adev->jpeg.inst->ras_poison_irq, 0);

		if (r)

			goto late_fini;

	}



	r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__JPEG,

				&jpeg_v4_0_3_aca_info, NULL);

	if (r)

drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h

+7 −0
Original line number Diff line number Diff line
@@ -46,6 +46,13 @@ 


#define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR				0x18000



enum amdgpu_jpeg_v4_0_3_sub_block {

	AMDGPU_JPEG_V4_0_3_JPEG0 = 0,

	AMDGPU_JPEG_V4_0_3_JPEG1,



	AMDGPU_JPEG_V4_0_3_MAX_SUB_BLOCK,

};



extern const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block;



void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring,