Commit 1b304561 authored by Austin Zheng's avatar Austin Zheng Committed by Alex Deucher
Browse files

drm/amd/display: DML21 Reintegration 



For various fixes to mcache_row_bytes calculation.

Reviewed-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Signed-off-by: default avatarAustin Zheng <Austin.Zheng@amd.com>
Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e8bffa52

drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

+0 −5
Original line number Diff line number Diff line
@@ -14,11 +14,6 @@ 


struct dml2_instance;



enum dml2_status {

	dml2_success = 0,

	dml2_error_generic = 1

};



enum dml2_project_id {

	dml2_project_invalid = 0,

	dml2_project_dcn4x_stage1 = 1,

drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c

+11 −11
Original line number Diff line number Diff line
@@ -44,7 +44,7 @@ struct dml2_core_ip_params core_dcn4_ip_caps_base = { 
	.dppclk_delay_scl_lb_only = 16,

	.dppclk_delay_cnvc_formatter = 28,

	.dppclk_delay_cnvc_cursor = 6,

	.cursor_buffer_size = 24,

	.cursor_buffer_size = 42,

	.cursor_chunk_size = 2,

	.dispclk_delay_subtotal = 125,

	.max_inter_dcn_tile_repeaters = 8,

drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.h

+0 −3
Original line number Diff line number Diff line
@@ -9,7 +9,4 @@ bool core_dcn4_mode_support(struct dml2_core_mode_support_in_out *in_out); 
bool core_dcn4_mode_programming(struct dml2_core_mode_programming_in_out *in_out);

bool core_dcn4_populate_informative(struct dml2_core_populate_informative_in_out *in_out);

bool core_dcn4_calculate_mcache_allocation(struct dml2_calculate_mcache_allocation_in_out *in_out);



bool core_dcn4_unit_test(void);



#endif

drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

+54 −40
Original line number Diff line number Diff line
@@ -2352,6 +2352,7 @@ static void calculate_mcache_row_bytes( 
	if (p->full_vp_height == 0 && p->full_vp_width == 0) {

		*p->num_mcaches = 0;

		*p->mcache_row_bytes = 0;

		*p->mcache_row_bytes_per_channel = 0;

	} else {

		blk_bytes = dml_get_tile_block_size_bytes(p->tiling_mode);








@@ -2420,15 +2421,18 @@ static void calculate_mcache_row_bytes(















		// If this mcache_row_bytes for the full viewport of the surface is less than or equal to mcache_bytes,









		// then one mcache can be used for this request stream. If not, it is useful to know the width of the viewport that can be supported in the mcache_bytes.









		if (p->gpuvm_enable || !p->surf_vert) {









			*p->mcache_row_bytes = mvmpg_per_row_ub * meta_per_mvmpg_per_channel_ub;









		if (p->gpuvm_enable || p->surf_vert) {









			*p->mcache_row_bytes_per_channel = mvmpg_per_row_ub * meta_per_mvmpg_per_channel_ub;









			*p->mcache_row_bytes = *p->mcache_row_bytes_per_channel * p->num_chans;









		} else { // horizontal and gpuvm disable









			*p->mcache_row_bytes = *p->meta_row_width_ub * p->blk_height * p->bytes_per_pixel / 256;









			*p->mcache_row_bytes = (unsigned int)math_ceil2((double)*p->mcache_row_bytes / p->num_chans, p->mcache_line_size_bytes);









			if (p->mcache_line_size_bytes != 0)









				*p->mcache_row_bytes_per_channel = (unsigned int)math_ceil2((double)*p->mcache_row_bytes / p->num_chans, p->mcache_line_size_bytes);









		}

















		*p->dcc_dram_bw_pref_overhead_factor = 1 + math_max2(1.0 / 256.0, *p->mcache_row_bytes / p->full_swath_bytes); // dcc_dr_oh_pref









		*p->num_mcaches = (unsigned int)math_ceil2((double)*p->mcache_row_bytes / p->mcache_size_bytes, 1);









		if (p->mcache_size_bytes != 0)









			*p->num_mcaches = (unsigned int)math_ceil2((double)*p->mcache_row_bytes_per_channel / p->mcache_size_bytes, 1);

















		mvmpg_per_mcache = p->mcache_size_bytes / meta_per_mvmpg_per_channel_ub;









		*p->mvmpg_per_mcache_lb = (unsigned int)math_floor2(mvmpg_per_mcache, 1);








@@ -2449,6 +2453,7 @@ static void calculate_mcache_row_bytes(















#ifdef __DML_VBA_DEBUG__









	dml2_printf("DML::%s: mcache_row_bytes = %u\n", __func__, *p->mcache_row_bytes);









	dml2_printf("DML::%s: mcache_row_bytes_per_channel = %u\n", __func__, *p->mcache_row_bytes_per_channel);









	dml2_printf("DML::%s: num_mcaches = %u\n", __func__, *p->num_mcaches);









#endif









	DML2_ASSERT(*p->num_mcaches > 0);








@@ -2465,11 +2470,13 @@ static void calculate_mcache_setting(















	*p->num_mcaches_l = 0;









	*p->mcache_row_bytes_l = 0;









	*p->mcache_row_bytes_per_channel_l = 0;









	*p->dcc_dram_bw_nom_overhead_factor_l = 1.0;









	*p->dcc_dram_bw_pref_overhead_factor_l = 1.0;

















	*p->num_mcaches_c = 0;









	*p->mcache_row_bytes_c = 0;









	*p->mcache_row_bytes_per_channel_c = 0;









	*p->dcc_dram_bw_nom_overhead_factor_c = 1.0;









	*p->dcc_dram_bw_pref_overhead_factor_c = 1.0;
















@@ -2505,6 +2512,7 @@ static void calculate_mcache_setting(







	// output









	l->l_p.num_mcaches = p->num_mcaches_l;









	l->l_p.mcache_row_bytes = p->mcache_row_bytes_l;









	l->l_p.mcache_row_bytes_per_channel = p->mcache_row_bytes_per_channel_l;









	l->l_p.dcc_dram_bw_nom_overhead_factor = p->dcc_dram_bw_nom_overhead_factor_l;









	l->l_p.dcc_dram_bw_pref_overhead_factor = p->dcc_dram_bw_pref_overhead_factor_l;









	l->l_p.mvmpg_width = &l->mvmpg_width_l;








@@ -2514,7 +2522,7 @@ static void calculate_mcache_setting(







	l->l_p.mvmpg_per_mcache_lb = &l->mvmpg_per_mcache_lb_l;

















	calculate_mcache_row_bytes(scratch, &l->l_p);









	dml2_assert(*p->num_mcaches_l > 0);









	DML2_ASSERT(*p->num_mcaches_l > 0);

















	if (l->is_dual_plane) {









		l->c_p.num_chans = p->num_chans;








@@ -2540,6 +2548,7 @@ static void calculate_mcache_setting(







		// output









		l->c_p.num_mcaches = p->num_mcaches_c;









		l->c_p.mcache_row_bytes = p->mcache_row_bytes_c;









		l->c_p.mcache_row_bytes_per_channel = p->mcache_row_bytes_per_channel_c;









		l->c_p.dcc_dram_bw_nom_overhead_factor = p->dcc_dram_bw_nom_overhead_factor_c;









		l->c_p.dcc_dram_bw_pref_overhead_factor = p->dcc_dram_bw_pref_overhead_factor_c;









		l->c_p.mvmpg_width = &l->mvmpg_width_c;








@@ -2549,12 +2558,12 @@ static void calculate_mcache_setting(







		l->c_p.mvmpg_per_mcache_lb = &l->mvmpg_per_mcache_lb_c;

















		calculate_mcache_row_bytes(scratch, &l->c_p);









		dml2_assert(*p->num_mcaches_c > 0);









		DML2_ASSERT(*p->num_mcaches_c > 0);









	}

















	// Sharing for iMALL access









	l->mcache_remainder_l = *p->mcache_row_bytes_l % p->mcache_size_bytes;









	l->mcache_remainder_c = *p->mcache_row_bytes_c % p->mcache_size_bytes;









	l->mcache_remainder_l = *p->mcache_row_bytes_per_channel_l % p->mcache_size_bytes;









	l->mcache_remainder_c = *p->mcache_row_bytes_per_channel_c % p->mcache_size_bytes;









	l->mvmpg_access_width_l = p->surf_vert ? l->mvmpg_height_l : l->mvmpg_width_l;









	l->mvmpg_access_width_c = p->surf_vert ? l->mvmpg_height_c : l->mvmpg_width_c;
















@@ -2577,12 +2586,15 @@ static void calculate_mcache_setting(







	if (l->is_dual_plane) {









		l->avg_mcache_element_size_c = l->meta_row_width_c / *p->num_mcaches_c;

















		/* if either remainder is 0, then mcache sharing is not needed or not possible due to full utilization */









		if (l->mcache_remainder_l && l->mcache_remainder_c) {









			if (!p->imall_enable || (*p->mall_comb_mcache_l == *p->mall_comb_mcache_c)) {









				l->lc_comb_last_mcache_size = (unsigned int)((l->mcache_remainder_l * (*p->mall_comb_mcache_l ? 2 : 1) * l->luma_time_factor) +









					(l->mcache_remainder_c * (*p->mall_comb_mcache_c ? 2 : 1)));









			}









			*p->lc_comb_mcache = (l->lc_comb_last_mcache_size <= p->mcache_size_bytes) && (*p->mall_comb_mcache_l == *p->mall_comb_mcache_c);









		}









	}

















#ifdef __DML_VBA_DEBUG__









	dml2_printf("DML::%s: imall_enable = %u\n", __func__, p->imall_enable);








@@ -2637,9 +2649,6 @@ static void calculate_mcache_setting(







	// Luma/Chroma combine in the last mcache









	// In the case of Luma/Chroma combine-mCache (with lc_comb_mcache==1), all mCaches except the last segment are filled as much as possible, when stay aligned to mvmpg boundary









	if (*p->lc_comb_mcache && l->is_dual_plane) {









		/* if luma and chroma planes share an mcache, increase total chroma mcache count */









		*p->num_mcaches_c = *p->num_mcaches_c + 1;

















		for (n = 0; n < *p->num_mcaches_l - 1; n++)









			p->mcache_offsets_l[n] = (n + 1) * l->mvmpg_per_mcache_lb_l * l->mvmpg_access_width_l;









		p->mcache_offsets_l[*p->num_mcaches_l - 1] = l->full_vp_access_width_l;








@@ -3400,7 +3409,7 @@ static void calculate_cursor_req_attributes(







	} else {









		if (cursor_width > 0) {









			dml2_printf("DML::%s: Invalid cursor_bpp = %d\n", __func__, cursor_bpp);









			dml2_assert(0);









			DML2_ASSERT(0);









		}









	}
















@@ -3443,7 +3452,7 @@ static void calculate_cursor_urgent_burst_factor(







		CursorBufferSizeInTime = LinesInCursorBuffer * LineTime;









		if (CursorBufferSizeInTime - UrgentLatency <= 0) {









			*NotEnoughUrgentLatencyHiding = 1;









			*UrgentBurstFactorCursor = 0;









			*UrgentBurstFactorCursor = 1;









		} else {









			*NotEnoughUrgentLatencyHiding = 0;









			*UrgentBurstFactorCursor = CursorBufferSizeInTime / (CursorBufferSizeInTime - UrgentLatency);








@@ -3506,7 +3515,7 @@ static void CalculateUrgentBurstFactor(







	DETBufferSizeInTimeLuma = math_floor2(LinesInDETLuma, SwathHeightY) * LineTime / VRatio;









	if (DETBufferSizeInTimeLuma - UrgentLatency <= 0) {









		*NotEnoughUrgentLatencyHiding = 1;









		*UrgentBurstFactorLuma = 0;









		*UrgentBurstFactorLuma = 1;









	} else {









		*UrgentBurstFactorLuma = DETBufferSizeInTimeLuma / (DETBufferSizeInTimeLuma - UrgentLatency);









	}








@@ -3517,7 +3526,7 @@ static void CalculateUrgentBurstFactor(







		DETBufferSizeInTimeChroma = math_floor2(LinesInDETChroma, SwathHeightC) * LineTime / VRatioC;









		if (DETBufferSizeInTimeChroma - UrgentLatency <= 0) {









			*NotEnoughUrgentLatencyHiding = 1;









			*UrgentBurstFactorChroma = 0;









			*UrgentBurstFactorChroma = 1;









		} else {









			*UrgentBurstFactorChroma = DETBufferSizeInTimeChroma / (DETBufferSizeInTimeChroma - UrgentLatency);









		}








@@ -5391,7 +5400,7 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch







	}

















	/* oto prefetch bw should be always be less than total vactive bw */









	DML2_ASSERT(s->prefetch_bw_oto < s->per_pipe_vactive_sw_bw * p->myPipe->DPPPerSurface);









	//DML2_ASSERT(s->prefetch_bw_oto < s->per_pipe_vactive_sw_bw * p->myPipe->DPPPerSurface);

















	s->prefetch_bw_oto = math_max2(s->per_pipe_vactive_sw_bw, s->prefetch_bw_oto) * p->mall_prefetch_sdp_overhead_factor;
















@@ -5801,7 +5810,7 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch







		dml2_printf("DML::%s: cursor_prefetch_bytes = %d\n", __func__, s->cursor_prefetch_bytes);









		dml2_printf("DML::%s: prefetch_cursor_bw = %f\n", __func__, *p->prefetch_cursor_bw);









#endif









		dml2_assert(*p->dst_y_prefetch < 64);









		DML2_ASSERT(*p->dst_y_prefetch < 64);

















		unsigned int min_lsw_required = (unsigned int)math_max2(2, p->tdlut_drain_time / s->LineTime);









		if (s->LinesToRequestPrefetchPixelData >= min_lsw_required && s->prefetch_bw_equ > 0) {








@@ -5994,7 +6003,7 @@ static unsigned int find_max_impact_plane(unsigned int this_plane_idx, unsigned







		}









	}









	if (max_idx <= 0) {









		dml2_assert(max_idx >= 0);









		DML2_ASSERT(max_idx >= 0);









		max_idx = this_plane_idx;









	}
















@@ -6341,7 +6350,7 @@ static void calculate_peak_bandwidth_required(







			dml2_printf("DML::%s: urg_bandwidth_required_qual[%s][%s]=%f\n", __func__, dml2_core_internal_soc_state_type_str(m), dml2_core_internal_bw_type_str(n), p->urg_bandwidth_required[m][n]);









			dml2_printf("DML::%s: non_urg_bandwidth_required%s[%s][%s]=%f\n", __func__, (p->inc_flip_bw ? "_flip" : ""), dml2_core_internal_soc_state_type_str(m), dml2_core_internal_bw_type_str(n), p->non_urg_bandwidth_required[m][n]);









#endif









			dml2_assert(p->urg_bandwidth_required[m][n] >= p->non_urg_bandwidth_required[m][n]);









			DML2_ASSERT(p->urg_bandwidth_required[m][n] >= p->non_urg_bandwidth_required[m][n]);









		}









	}









}








@@ -6473,7 +6482,7 @@ static void calculate_immediate_flip_bandwidth_support(







		dml2_printf("DML::%s: urg_bandwidth_required_flip = %f\n", __func__, urg_bandwidth_required_flip[eval_state][n]);









		dml2_printf("DML::%s: flip_bandwidth_support_ok = %d\n", __func__, *flip_bandwidth_support_ok);









#endif









		dml2_assert(urg_bandwidth_required_flip[eval_state][n] >= non_urg_bandwidth_required_flip[eval_state][n]);









		DML2_ASSERT(urg_bandwidth_required_flip[eval_state][n] >= non_urg_bandwidth_required_flip[eval_state][n]);









	}

















	*frac_urg_bandwidth_flip = (frac_urg_bw_flip_sdp > frac_urg_bw_flip_dram) ? frac_urg_bw_flip_sdp : frac_urg_bw_flip_dram;








@@ -6587,7 +6596,7 @@ static void CalculateFlipSchedule(







#ifdef __DML_VBA_DEBUG__









		dml2_printf("DML::%s: min_row_time = %f\n", __func__, l->min_row_time);









#endif









		dml2_assert(l->min_row_time > 0);









		DML2_ASSERT(l->min_row_time > 0);

















		if (use_lb_flip_bw) {









			// For mode check, calculation the flip bw requirement with worst case flip time








@@ -7163,7 +7172,8 @@ static unsigned int get_active_min_uclk_dpm_index(unsigned long uclk_freq_khz, c







		}









	}

















	dml2_assert(clk_entry_found);









	if (!clk_entry_found)









		DML2_ASSERT(clk_entry_found);









#if defined(__DML_VBA_DEBUG__)









	dml2_printf("DML::%s: uclk_freq_khz = %ld\n", __func__, uclk_freq_khz);









	dml2_printf("DML::%s: index = %d\n", __func__, i);








@@ -8772,11 +8782,13 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out















			calculate_mcache_setting_params->num_mcaches_l = &mode_lib->ms.num_mcaches_l[k];









			calculate_mcache_setting_params->mcache_row_bytes_l = &mode_lib->ms.mcache_row_bytes_l[k];









			calculate_mcache_setting_params->mcache_row_bytes_per_channel_l = &mode_lib->ms.mcache_row_bytes_per_channel_l[k];









			calculate_mcache_setting_params->mcache_offsets_l = mode_lib->ms.mcache_offsets_l[k];









			calculate_mcache_setting_params->mcache_shift_granularity_l = &mode_lib->ms.mcache_shift_granularity_l[k];

















			calculate_mcache_setting_params->num_mcaches_c = &mode_lib->ms.num_mcaches_c[k];









			calculate_mcache_setting_params->mcache_row_bytes_c = &mode_lib->ms.mcache_row_bytes_c[k];









			calculate_mcache_setting_params->mcache_row_bytes_per_channel_c = &mode_lib->ms.mcache_row_bytes_per_channel_c[k];









			calculate_mcache_setting_params->mcache_offsets_c = mode_lib->ms.mcache_offsets_c[k];









			calculate_mcache_setting_params->mcache_shift_granularity_c = &mode_lib->ms.mcache_shift_granularity_c[k];
















@@ -10430,13 +10442,13 @@ static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex















	for (k = 0; k < s->num_active_planes; ++k) {









		unsigned int stream_index = display_cfg->plane_descriptors[k].stream_index;









		dml2_assert(cfg_support_info->stream_support_info[stream_index].odms_used <= 4);









		dml2_assert(cfg_support_info->stream_support_info[stream_index].num_odm_output_segments == 4 ||









		DML2_ASSERT(cfg_support_info->stream_support_info[stream_index].odms_used <= 4);









		DML2_ASSERT(cfg_support_info->stream_support_info[stream_index].num_odm_output_segments == 4 ||









					cfg_support_info->stream_support_info[stream_index].num_odm_output_segments == 2 ||









					cfg_support_info->stream_support_info[stream_index].num_odm_output_segments == 1);

















		if (cfg_support_info->stream_support_info[stream_index].odms_used > 1)









			dml2_assert(cfg_support_info->stream_support_info[stream_index].num_odm_output_segments == 1);









			DML2_ASSERT(cfg_support_info->stream_support_info[stream_index].num_odm_output_segments == 1);

















		switch (cfg_support_info->stream_support_info[stream_index].odms_used) {









		case (4):








@@ -10462,7 +10474,7 @@ static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex







	for (k = 0; k < s->num_active_planes; ++k) {









		mode_lib->mp.NoOfDPP[k] = cfg_support_info->plane_support_info[k].dpps_used;









		mode_lib->mp.Dppclk[k] = programming->plane_programming[k].min_clocks.dcn4x.dppclk_khz / 1000.0;









		dml2_assert(mode_lib->mp.Dppclk[k] > 0);









		DML2_ASSERT(mode_lib->mp.Dppclk[k] > 0);









	}

















	for (k = 0; k < s->num_active_planes; ++k) {








@@ -10474,14 +10486,14 @@ static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex







	mode_lib->mp.Dispclk = programming->min_clocks.dcn4x.dispclk_khz / 1000.0;









	mode_lib->mp.DCFCLKDeepSleep = programming->min_clocks.dcn4x.deepsleep_dcfclk_khz / 1000.0;

















	dml2_assert(mode_lib->mp.Dcfclk > 0);









	dml2_assert(mode_lib->mp.FabricClock > 0);









	dml2_assert(mode_lib->mp.dram_bw_mbps > 0);









	dml2_assert(mode_lib->mp.uclk_freq_mhz > 0);









	dml2_assert(mode_lib->mp.GlobalDPPCLK > 0);









	dml2_assert(mode_lib->mp.Dispclk > 0);









	dml2_assert(mode_lib->mp.DCFCLKDeepSleep > 0);









	dml2_assert(s->SOCCLK > 0);









	DML2_ASSERT(mode_lib->mp.Dcfclk > 0);









	DML2_ASSERT(mode_lib->mp.FabricClock > 0);









	DML2_ASSERT(mode_lib->mp.dram_bw_mbps > 0);









	DML2_ASSERT(mode_lib->mp.uclk_freq_mhz > 0);









	DML2_ASSERT(mode_lib->mp.GlobalDPPCLK > 0);









	DML2_ASSERT(mode_lib->mp.Dispclk > 0);









	DML2_ASSERT(mode_lib->mp.DCFCLKDeepSleep > 0);









	DML2_ASSERT(s->SOCCLK > 0);

















#ifdef __DML_VBA_DEBUG__









	dml2_printf("DML::%s: num_active_planes = %u\n", __func__, s->num_active_planes);








@@ -10869,11 +10881,13 @@ static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex















			calculate_mcache_setting_params->num_mcaches_l = &mode_lib->mp.num_mcaches_l[k];









			calculate_mcache_setting_params->mcache_row_bytes_l = &mode_lib->mp.mcache_row_bytes_l[k];









			calculate_mcache_setting_params->mcache_row_bytes_per_channel_l = &mode_lib->mp.mcache_row_bytes_per_channel_l[k];









			calculate_mcache_setting_params->mcache_offsets_l = mode_lib->mp.mcache_offsets_l[k];









			calculate_mcache_setting_params->mcache_shift_granularity_l = &mode_lib->mp.mcache_shift_granularity_l[k];

















			calculate_mcache_setting_params->num_mcaches_c = &mode_lib->mp.num_mcaches_c[k];









			calculate_mcache_setting_params->mcache_row_bytes_c = &mode_lib->mp.mcache_row_bytes_c[k];









			calculate_mcache_setting_params->mcache_row_bytes_per_channel_c = &mode_lib->mp.mcache_row_bytes_per_channel_c[k];









			calculate_mcache_setting_params->mcache_offsets_c = mode_lib->mp.mcache_offsets_c[k];









			calculate_mcache_setting_params->mcache_shift_granularity_c = &mode_lib->mp.mcache_shift_granularity_c[k];
















@@ -11585,7 +11599,6 @@ static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex







			calculate_peak_bandwidth_params->surface_read_bandwidth_c = mode_lib->mp.vactive_sw_bw_c;









			calculate_peak_bandwidth_params->prefetch_bandwidth_l = mode_lib->mp.RequiredPrefetchPixelDataBWLuma;









			calculate_peak_bandwidth_params->prefetch_bandwidth_c = mode_lib->mp.RequiredPrefetchPixelDataBWChroma;









			calculate_peak_bandwidth_params->prefetch_bandwidth_oto = s->dummy_single_array[k];









			calculate_peak_bandwidth_params->excess_vactive_fill_bw_l = mode_lib->mp.excess_vactive_fill_bw_l;









			calculate_peak_bandwidth_params->excess_vactive_fill_bw_c = mode_lib->mp.excess_vactive_fill_bw_c;









			calculate_peak_bandwidth_params->cursor_bw = mode_lib->mp.cursor_bw;








@@ -11593,6 +11606,7 @@ static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex







			calculate_peak_bandwidth_params->meta_row_bw = mode_lib->mp.meta_row_bw;









			calculate_peak_bandwidth_params->prefetch_cursor_bw = mode_lib->mp.prefetch_cursor_bw;









			calculate_peak_bandwidth_params->prefetch_vmrow_bw = mode_lib->mp.prefetch_vmrow_bw;









			calculate_peak_bandwidth_params->prefetch_bandwidth_oto = s->dummy_single_array[0];









			calculate_peak_bandwidth_params->flip_bw = mode_lib->mp.final_flip_bw;









			calculate_peak_bandwidth_params->urgent_burst_factor_l = mode_lib->mp.UrgentBurstFactorLuma;









			calculate_peak_bandwidth_params->urgent_burst_factor_c = mode_lib->mp.UrgentBurstFactorChroma;








@@ -12398,7 +12412,7 @@ static void rq_dlg_get_dlg_reg(







	dml2_printf("DML_DLG::%s: Calculation for pipe_idx=%d\n", __func__, pipe_idx);

















	l->plane_idx = dml_get_plane_idx(mode_lib, pipe_idx);









	dml2_assert(l->plane_idx < DML2_MAX_PLANES);









	DML2_ASSERT(l->plane_idx < DML2_MAX_PLANES);

















	l->source_format = dml2_444_8;









	l->odm_mode = dml2_odm_mode_bypass;

























drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared.c
deleted100644 → 0



+0
−12413




























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