Commit 1b4bb451 authored by Michal Wilczynski's avatar Michal Wilczynski Committed by Drew Fustini
Browse files

dt-bindings: clock: thead: Add TH1520 VO clock controller 



Add device tree bindings for the TH1520 Video Output (VO) subsystem
clock controller. The VO sub-system manages clock gates for multimedia
components including HDMI, MIPI, and GPU.

Document the VIDEO_PLL requirements for the VO clock controller, which
receives its input from the AP clock controller. The VIDEO_PLL is a
Silicon Creations Sigma-Delta (integer) PLL typically running at 792 MHz
with maximum FOUTVCO of 2376 MHz.

This binding complements the existing AP sub-system clock controller
which manages CPU, DPU, GMAC and TEE PLLs.

Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: default avatarConor Dooley <conor.dooley@microchip.com>
Signed-off-by: default avatarMichal Wilczynski <m.wilczynski@samsung.com>
Reviewed-by: default avatarDrew Fustini <drew@pdp7.com>
Signed-off-by: default avatarDrew Fustini <drew@pdp7.com>
parent 0af2f6be

Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml

+14 −3
Original line number Diff line number Diff line
@@ -8,7 +8,8 @@ title: T-HEAD TH1520 AP sub-system clock controller 


description: |

  The T-HEAD TH1520 AP sub-system clock controller configures the

  CPU, DPU, GMAC and TEE PLLs.

  CPU, DPU, GMAC and TEE PLLs. Additionally the VO subsystem configures

  the clock gates for the HDMI, MIPI and the GPU.



  SoC reference manual

  https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf
@@ -20,14 +21,24 @@ maintainers: 


properties:

  compatible:

    const: thead,th1520-clk-ap

    enum:

      - thead,th1520-clk-ap

      - thead,th1520-clk-vo



  reg:

    maxItems: 1



  clocks:

    items:

      - description: main oscillator (24MHz)

      - description: |

          One input clock:

          - For "thead,th1520-clk-ap": the clock input must be the 24 MHz

            main oscillator.

          - For "thead,th1520-clk-vo": the clock input must be the VIDEO_PLL,

            which is configured by the AP clock controller. According to the

            TH1520 manual, VIDEO_PLL is a Silicon Creations Sigma-Delta PLL

            (integer PLL) typically running at 792 MHz (FOUTPOSTDIV), with

            a maximum FOUTVCO of 2376 MHz.



  "#clock-cells":

    const: 1

include/dt-bindings/clock/thead,th1520-clk-ap.h

+34 −0
Original line number Diff line number Diff line
@@ -93,4 +93,38 @@ 
#define CLK_SRAM3		83

#define CLK_PLL_GMAC_100M	84

#define CLK_UART_SCLK		85



/* VO clocks */

#define CLK_AXI4_VO_ACLK		0

#define CLK_GPU_MEM			1

#define CLK_GPU_CORE			2

#define CLK_GPU_CFG_ACLK		3

#define CLK_DPU_PIXELCLK0		4

#define CLK_DPU_PIXELCLK1		5

#define CLK_DPU_HCLK			6

#define CLK_DPU_ACLK			7

#define CLK_DPU_CCLK			8

#define CLK_HDMI_SFR			9

#define CLK_HDMI_PCLK			10

#define CLK_HDMI_CEC			11

#define CLK_MIPI_DSI0_PCLK		12

#define CLK_MIPI_DSI1_PCLK		13

#define CLK_MIPI_DSI0_CFG		14

#define CLK_MIPI_DSI1_CFG		15

#define CLK_MIPI_DSI0_REFCLK		16

#define CLK_MIPI_DSI1_REFCLK		17

#define CLK_HDMI_I2S			18

#define CLK_X2H_DPU1_ACLK		19

#define CLK_X2H_DPU_ACLK		20

#define CLK_AXI4_VO_PCLK		21

#define CLK_IOPMP_VOSYS_DPU_PCLK	22

#define CLK_IOPMP_VOSYS_DPU1_PCLK	23

#define CLK_IOPMP_VOSYS_GPU_PCLK	24

#define CLK_IOPMP_DPU1_ACLK		25

#define CLK_IOPMP_DPU_ACLK		26

#define CLK_IOPMP_GPU_ACLK		27

#define CLK_MIPIDSI0_PIXCLK		28

#define CLK_MIPIDSI1_PIXCLK		29

#define CLK_HDMI_PIXCLK			30



#endif