Commit 1b85f96d authored by Mika Kahola's avatar Mika Kahola
Browse files

drm/i915/lt_phy: Drop 27.2 MHz rate 



Drop 27.2 MHz PLL table as with these PLL dividers
the port clock will be incorrectly calculated to 27.0 MHz.
For 27.2 MHz rate the PLl dividers are calculated
algorithmically making PLL table for this rate redundant.

Signed-off-by: default avatarMika Kahola <mika.kahola@intel.com>
Reviewed-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260119093757.2850233-15-mika.kahola@intel.com
parent 4fa24458

drivers/gpu/drm/i915/display/intel_lt_phy.c

+0 −55
Original line number Diff line number Diff line
@@ -803,60 +803,6 @@ static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_252 = { 
	},

};



static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_272 = {

	.clock = 27200,

	.config = {

		0x84,

		0x2d,

		0x0,

	},

	.addr_msb = {

		0x87,

		0x87,

		0x87,

		0x87,

		0x88,

		0x88,

		0x88,

		0x88,

		0x88,

		0x88,

		0x88,

		0x88,

		0x88,

	},

	.addr_lsb = {

		0x10,

		0x0c,

		0x14,

		0xe4,

		0x0c,

		0x10,

		0x14,

		0x18,

		0x48,

		0x40,

		0x4c,

		0x24,

		0x44,

	},

	.data = {

		{ 0x0,  0x4c, 0x2,  0x0  },

		{ 0x0b, 0x15, 0x26, 0xa0 },

		{ 0x60, 0x0,  0x0,  0x0  },

		{ 0x8,  0x4,  0x96, 0x28 },

		{ 0xfa, 0x0c, 0x84, 0x11 },

		{ 0x80, 0x0f, 0xd9, 0x53 },

		{ 0x86, 0x0,  0x0,  0x0  },

		{ 0x1,  0xa0, 0x1,  0x0  },

		{ 0x4b, 0x0,  0x0,  0x0  },

		{ 0x28, 0x0,  0x0,  0x0  },

		{ 0x0,  0x14, 0x2a, 0x14 },

		{ 0x0,  0x0,  0x0,  0x0  },

		{ 0x0,  0x0,  0x0,  0x0  },

	},

};



static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_742p5 = {

	.clock = 74250,

	.config = {
@@ -1021,7 +967,6 @@ static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_5p94 = { 


static const struct intel_lt_phy_pll_params xe3plpd_lt_hdmi_tables[] = {

	LT_PHY_PLL_HDMI_PARAMS(25200, xe3plpd_lt_hdmi_252),

	LT_PHY_PLL_HDMI_PARAMS(27200, xe3plpd_lt_hdmi_272),

	LT_PHY_PLL_HDMI_PARAMS(74250, xe3plpd_lt_hdmi_742p5),

	LT_PHY_PLL_HDMI_PARAMS(148500, xe3plpd_lt_hdmi_1p485),

	LT_PHY_PLL_HDMI_PARAMS(594000, xe3plpd_lt_hdmi_5p94),