Commit 1b908deb authored by Tony Luck's avatar Tony Luck Committed by Borislav Petkov (AMD)
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x86/resctrl: Fix unused variable warning in cache_alloc_hsw_probe() 



In a "W=1" build gcc throws a warning:

  arch/x86/kernel/cpu/resctrl/core.c: In function ‘cache_alloc_hsw_probe’:
  arch/x86/kernel/cpu/resctrl/core.c:139:16: warning: variable ‘h’ set but not used

Switch from wrmsr_safe() to wrmsrl_safe(), and from rdmsr() to rdmsrl()
using a single u64 argument for the MSR value instead of the pair of u32
for the high and low halves.

Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: default avatarBabu Moger <babu.moger@amd.com>
Acked-by: default avatarReinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/r/ZULCd/TGJL9Dmncf@agluck-desk3
parent 6613476e

arch/x86/kernel/cpu/resctrl/core.c

+4 −4
Original line number Diff line number Diff line
@@ -136,15 +136,15 @@ static inline void cache_alloc_hsw_probe(void) 
{

	struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_L3];

	struct rdt_resource *r  = &hw_res->r_resctrl;

	u32 l, h, max_cbm = BIT_MASK(20) - 1;

	u64 max_cbm = BIT_ULL_MASK(20) - 1, l3_cbm_0;



	if (wrmsr_safe(MSR_IA32_L3_CBM_BASE, max_cbm, 0))

	if (wrmsrl_safe(MSR_IA32_L3_CBM_BASE, max_cbm))

		return;



	rdmsr(MSR_IA32_L3_CBM_BASE, l, h);

	rdmsrl(MSR_IA32_L3_CBM_BASE, l3_cbm_0);



	/* If all the bits were set in MSR, return success */

	if (l != max_cbm)

	if (l3_cbm_0 != max_cbm)

		return;



	hw_res->num_closid = 4;