Commit 1ba1a4a9 authored by Yuji Ishikawa's avatar Yuji Ishikawa Committed by David S. Miller
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net: stmmac: dwmac-visconti: Fix bit definitions for ETHER_CLK_SEL 



just 0 should be used to represent cleared bits

* ETHER_CLK_SEL_DIV_SEL_20
* ETHER_CLK_SEL_TX_CLK_EXT_SEL_IN
* ETHER_CLK_SEL_RX_CLK_EXT_SEL_IN
* ETHER_CLK_SEL_TX_CLK_O_TX_I
* ETHER_CLK_SEL_RMII_CLK_SEL_IN

Fixes: b38dd98f ("net: stmmac: Add Toshiba Visconti SoCs glue driver")
Signed-off-by: default avatarYuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>
Reviewed-by: default avatarNobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 6cee105e

drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c

+5 −5
Original line number Diff line number Diff line
@@ -22,21 +22,21 @@ 
#define ETHER_CLK_SEL_RMII_CLK_EN BIT(2)

#define ETHER_CLK_SEL_RMII_CLK_RST BIT(3)

#define ETHER_CLK_SEL_DIV_SEL_2 BIT(4)

#define ETHER_CLK_SEL_DIV_SEL_20 BIT(0)

#define ETHER_CLK_SEL_DIV_SEL_20 0

#define ETHER_CLK_SEL_FREQ_SEL_125M	(BIT(9) | BIT(8))

#define ETHER_CLK_SEL_FREQ_SEL_50M	BIT(9)

#define ETHER_CLK_SEL_FREQ_SEL_25M	BIT(8)

#define ETHER_CLK_SEL_FREQ_SEL_2P5M	0

#define ETHER_CLK_SEL_TX_CLK_EXT_SEL_IN BIT(0)

#define ETHER_CLK_SEL_TX_CLK_EXT_SEL_IN 0

#define ETHER_CLK_SEL_TX_CLK_EXT_SEL_TXC BIT(10)

#define ETHER_CLK_SEL_TX_CLK_EXT_SEL_DIV BIT(11)

#define ETHER_CLK_SEL_RX_CLK_EXT_SEL_IN  BIT(0)

#define ETHER_CLK_SEL_RX_CLK_EXT_SEL_IN  0

#define ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC BIT(12)

#define ETHER_CLK_SEL_RX_CLK_EXT_SEL_DIV BIT(13)

#define ETHER_CLK_SEL_TX_CLK_O_TX_I	 BIT(0)

#define ETHER_CLK_SEL_TX_CLK_O_TX_I	 0

#define ETHER_CLK_SEL_TX_CLK_O_RMII_I	 BIT(14)

#define ETHER_CLK_SEL_TX_O_E_N_IN	 BIT(15)

#define ETHER_CLK_SEL_RMII_CLK_SEL_IN	 BIT(0)

#define ETHER_CLK_SEL_RMII_CLK_SEL_IN	 0

#define ETHER_CLK_SEL_RMII_CLK_SEL_RX_C	 BIT(16)



#define ETHER_CLK_SEL_RX_TX_CLK_EN (ETHER_CLK_SEL_RX_CLK_EN | ETHER_CLK_SEL_TX_CLK_EN)