Loading arch/mips/kernel/smp_mt.c +0 −29 Original line number Diff line number Diff line Loading @@ -102,35 +102,6 @@ void __init sanitize_tlb_entries(void) clear_c0_mvpcontrol(MVPCONTROL_VPC); } #if 0 /* * Use c0_MVPConf0 to find out how many CPUs are available, setting up * phys_cpu_present_map and the logical/physical mappings. */ void __init prom_build_cpu_map(void) { int i, num, ncpus; cpus_clear(phys_cpu_present_map); /* assume we boot on cpu 0.... */ cpu_set(0, phys_cpu_present_map); __cpu_number_map[0] = 0; __cpu_logical_map[0] = 0; if (cpu_has_mipsmt) { ncpus = ((read_c0_mvpconf0() & (MVPCONF0_PVPE)) >> MVPCONF0_PVPE_SHIFT) + 1; for (i=1, num=0; i< NR_CPUS && i<ncpus; i++) { cpu_set(i, phys_cpu_present_map); __cpu_number_map[i] = ++num; __cpu_logical_map[num] = i; } printk(KERN_INFO "%i available secondary CPU(s)\n", num); } } #endif static void ipi_resched_dispatch (struct pt_regs *regs) { do_IRQ(MIPS_CPU_IPI_RESCHED_IRQ, regs); Loading Loading
arch/mips/kernel/smp_mt.c +0 −29 Original line number Diff line number Diff line Loading @@ -102,35 +102,6 @@ void __init sanitize_tlb_entries(void) clear_c0_mvpcontrol(MVPCONTROL_VPC); } #if 0 /* * Use c0_MVPConf0 to find out how many CPUs are available, setting up * phys_cpu_present_map and the logical/physical mappings. */ void __init prom_build_cpu_map(void) { int i, num, ncpus; cpus_clear(phys_cpu_present_map); /* assume we boot on cpu 0.... */ cpu_set(0, phys_cpu_present_map); __cpu_number_map[0] = 0; __cpu_logical_map[0] = 0; if (cpu_has_mipsmt) { ncpus = ((read_c0_mvpconf0() & (MVPCONF0_PVPE)) >> MVPCONF0_PVPE_SHIFT) + 1; for (i=1, num=0; i< NR_CPUS && i<ncpus; i++) { cpu_set(i, phys_cpu_present_map); __cpu_number_map[i] = ++num; __cpu_logical_map[num] = i; } printk(KERN_INFO "%i available secondary CPU(s)\n", num); } } #endif static void ipi_resched_dispatch (struct pt_regs *regs) { do_IRQ(MIPS_CPU_IPI_RESCHED_IRQ, regs); Loading