Commit 1bf4adbb authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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clk: renesas: r9a09g056: Add clocks and resets for Mali-G31 GPU 



Add clock and reset support for the Mali-G31 GPU on the Renesas RZ/V2N
(R9A09G056) SoC. This includes adding clock sources required for the
module clocks.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250513154635.273664-6-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent e018f9f8

drivers/clk/renesas/r9a09g056-cpg.c

+16 −0
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ enum clk_ids { 
	CLK_PLLDTY,

	CLK_PLLCA55,

	CLK_PLLETH,

	CLK_PLLGPU,



	/* Internal Core Clocks */

	CLK_PLLCM33_DIV16,
@@ -36,6 +37,7 @@ enum clk_ids { 
	CLK_PLLCLN_DIV8,

	CLK_PLLCLN_DIV16,

	CLK_PLLDTY_ACPU,

	CLK_PLLDTY_ACPU_DIV2,

	CLK_PLLDTY_ACPU_DIV4,

	CLK_PLLDTY_DIV8,

	CLK_PLLETH_DIV_250_FIX,
@@ -46,6 +48,7 @@ enum clk_ids { 
	CLK_SMUX2_GBE0_RXCLK,

	CLK_SMUX2_GBE1_TXCLK,

	CLK_SMUX2_GBE1_RXCLK,

	CLK_PLLGPU_GEAR,



	/* Module Clocks */

	MOD_CLK_BASE,
@@ -93,6 +96,7 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = { 
	DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),

	DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),

	DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),

	DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU),



	/* Internal Core Clocks */

	DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
@@ -102,6 +106,7 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = { 
	DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),



	DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),

	DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),

	DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),

	DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
@@ -116,6 +121,8 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = { 
	DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),

	DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),



	DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),



	/* Core Clocks */

	DEF_FIXED("sys_0_pclk", R9A09G056_SYS_0_PCLK, CLK_QEXTAL, 1, 1),

	DEF_DDIV("ca55_0_coreclk0", R9A09G056_CA55_0_CORE_CLK0, CLK_PLLCA55,
@@ -236,6 +243,12 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = { 
						BUS_MSTOP(8, BIT(6))),

	DEF_MOD("gbeth_1_aclk_i",		CLK_PLLDTY_DIV8, 12, 3, 6, 3,

						BUS_MSTOP(8, BIT(6))),

	DEF_MOD("gpu_0_clk",			CLK_PLLGPU_GEAR, 15, 0, 7, 16,

						BUS_MSTOP(3, BIT(4))),

	DEF_MOD("gpu_0_axi_clk",		CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,

						BUS_MSTOP(3, BIT(4))),

	DEF_MOD("gpu_0_ace_clk",		CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,

						BUS_MSTOP(3, BIT(4))),

};



static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
@@ -269,6 +282,9 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = { 
	DEF_RST(10, 9, 4, 26),		/* SDHI_2_IXRST */

	DEF_RST(11, 0, 5, 1),		/* GBETH_0_ARESETN_I */

	DEF_RST(11, 1, 5, 2),		/* GBETH_1_ARESETN_I */

	DEF_RST(13, 13, 6, 14),		/* GPU_0_RESETN */

	DEF_RST(13, 14, 6, 15),		/* GPU_0_AXI_RESETN */

	DEF_RST(13, 15, 6, 16),		/* GPU_0_ACE_RESETN */

};



const struct rzv2h_cpg_info r9a09g056_cpg_info __initconst = {