Commit 1c388da5 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/mtl: Add engine TLB invalidation 



MTL's primary GT can continue to use the same engine TLB invalidation
programming as past Xe_HP-based platforms.  However the media GT needs
some special handling:
 * Invalidation registers on the media GT are singleton registers
   (unlike the primary GT where they are still MCR).
 * Since the GSC is now exposed as an engine, there's a new register to
   use for TLB invalidation.  The offset is identical to the compute
   engine offset, but this is expected --- compute engines only exist on
   the primary GT while the GSC only exists on the media GT.
 * Although there's only a single GSC engine instance, it inexplicably
   uses bit 1 to request invalidations rather than bit 0.

v2:
 - Add a 'regs == xelpmp_regs' condition to the GSC instance handling.
   If the registers change on a future platform, the GSC-specific
   handling is likely to change as well.  (Andrzej)

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarAndrzej Hajda <andrzej.hajda@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230224012009.3594691-1-matthew.d.roper@intel.com
parent ba8ff971

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+37 −15
Original line number Diff line number Diff line
@@ -1166,6 +1166,11 @@ static int intel_engine_init_tlb_invalidation(struct intel_engine_cs *engine) 
		[COPY_ENGINE_CLASS].mcr_reg	  = XEHP_BLT_TLB_INV_CR,

		[COMPUTE_CLASS].mcr_reg		  = XEHP_COMPCTX_TLB_INV_CR,

	};

	static const union intel_engine_tlb_inv_reg xelpmp_regs[] = {

		[VIDEO_DECODE_CLASS].reg	  = GEN12_VD_TLB_INV_CR,

		[VIDEO_ENHANCEMENT_CLASS].reg     = GEN12_VE_TLB_INV_CR,

		[OTHER_CLASS].reg		  = XELPMP_GSC_TLB_INV_CR,

	};

	struct drm_i915_private *i915 = engine->i915;

	const unsigned int instance = engine->instance;

	const unsigned int class = engine->class;
@@ -1185,7 +1190,15 @@ static int intel_engine_init_tlb_invalidation(struct intel_engine_cs *engine) 
	 * 12.00 -> 12.50 transition multi cast handling is required too.

	 */



	if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 50) ||

	if (engine->gt->type == GT_MEDIA) {

		if (MEDIA_VER_FULL(i915) == IP_VER(13, 0)) {

			regs = xelpmp_regs;

			num = ARRAY_SIZE(xelpmp_regs);

		}

	} else {

		if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 71) ||

		    GRAPHICS_VER_FULL(i915) == IP_VER(12, 70) ||

		    GRAPHICS_VER_FULL(i915) == IP_VER(12, 50) ||

		    GRAPHICS_VER_FULL(i915) == IP_VER(12, 55)) {

			regs = xehp_regs;

			num = ARRAY_SIZE(xehp_regs);
@@ -1199,6 +1212,7 @@ static int intel_engine_init_tlb_invalidation(struct intel_engine_cs *engine) 
		} else if (GRAPHICS_VER(i915) < 8) {

			return 0;

		}

	}



	if (gt_WARN_ONCE(engine->gt, !num,

			 "Platform does not implement TLB invalidation!"))
@@ -1212,7 +1226,14 @@ static int intel_engine_init_tlb_invalidation(struct intel_engine_cs *engine) 


	reg = regs[class];



	if (regs == gen8_regs && class == VIDEO_DECODE_CLASS && instance == 1) {

	if (regs == xelpmp_regs && class == OTHER_CLASS) {

		/*

		 * There's only a single GSC instance, but it uses register bit

		 * 1 instead of either 0 or OTHER_GSC_INSTANCE.

		 */

		GEM_WARN_ON(instance != OTHER_GSC_INSTANCE);

		val = 1;

	} else if (regs == gen8_regs && class == VIDEO_DECODE_CLASS && instance == 1) {

		reg.reg = GEN8_M2TCR;

		val = 0;

	} else {
@@ -1228,7 +1249,8 @@ static int intel_engine_init_tlb_invalidation(struct intel_engine_cs *engine) 
	if (GRAPHICS_VER(i915) >= 12 &&

	    (engine->class == VIDEO_DECODE_CLASS ||

	     engine->class == VIDEO_ENHANCEMENT_CLASS ||

	     engine->class == COMPUTE_CLASS))

	     engine->class == COMPUTE_CLASS ||

	     engine->class == OTHER_CLASS))

		engine->tlb_inv.request = _MASKED_BIT_ENABLE(val);

	else

		engine->tlb_inv.request = val;

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -1090,6 +1090,7 @@ 
#define XEHP_BLT_TLB_INV_CR			MCR_REG(0xcee4)

#define GEN12_COMPCTX_TLB_INV_CR		_MMIO(0xcf04)

#define XEHP_COMPCTX_TLB_INV_CR			MCR_REG(0xcf04)

#define XELPMP_GSC_TLB_INV_CR			_MMIO(0xcf04)   /* media GT only */



#define XEHP_MERT_MOD_CTRL			MCR_REG(0xcf28)

#define RENDER_MOD_CTRL				MCR_REG(0xcf2c)