Commit 1c5a0b55 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files
KVM/arm64 changes for 6.11

 - Initial infrastructure for shadow stage-2 MMUs, as part of nested
   virtualization enablement

 - Support for userspace changes to the guest CTR_EL0 value, enabling
   (in part) migration of VMs between heterogenous hardware

 - Fixes + improvements to pKVM's FF-A proxy, adding support for v1.1 of
   the protocol

 - FPSIMD/SVE support for nested, including merged trap configuration
   and exception routing

 - New command-line parameter to control the WFx trap behavior under KVM

 - Introduce kCFI hardening in the EL2 hypervisor

 - Fixes + cleanups for handling presence/absence of FEAT_TCRX

 - Miscellaneous fixes + documentation updates
parents c8b8b819 bb032b23
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+18 −0
Original line number Diff line number Diff line
@@ -2720,6 +2720,24 @@
			[KVM,ARM,EARLY] Allow use of GICv4 for direct
			injection of LPIs.

	kvm-arm.wfe_trap_policy=
			[KVM,ARM] Control when to set WFE instruction trap for
			KVM VMs. Traps are allowed but not guaranteed by the
			CPU architecture.

			trap: set WFE instruction trap

			notrap: clear WFE instruction trap

	kvm-arm.wfi_trap_policy=
			[KVM,ARM] Control when to set WFI instruction trap for
			KVM VMs. Traps are allowed but not guaranteed by the
			CPU architecture.

			trap: set WFI instruction trap

			notrap: clear WFI instruction trap

	kvm_cma_resv_ratio=n [PPC,EARLY]
			Reserves given percentage from system memory area for
			contiguous memory allocation for KVM hash pagetable
+5 −5
Original line number Diff line number Diff line
@@ -891,12 +891,12 @@ like this::

The irq_type field has the following values:

- irq_type[0]:
- KVM_ARM_IRQ_TYPE_CPU:
	       out-of-kernel GIC: irq_id 0 is IRQ, irq_id 1 is FIQ
- irq_type[1]:
- KVM_ARM_IRQ_TYPE_SPI:
	       in-kernel GIC: SPI, irq_id between 32 and 1019 (incl.)
               (the vcpu_index field is ignored)
- irq_type[2]:
- KVM_ARM_IRQ_TYPE_PPI:
	       in-kernel GIC: PPI, irq_id between 16 and 31 (incl.)

(The irq_id field thus corresponds nicely to the IRQ ID in the ARM GIC specs)
@@ -1927,7 +1927,7 @@ flags:

If KVM_MSI_VALID_DEVID is set, devid contains a unique device identifier
for the device that wrote the MSI message.  For PCI, this is usually a
BFD identifier in the lower 16 bits.
BDF identifier in the lower 16 bits.

On x86, address_hi is ignored unless the KVM_X2APIC_API_USE_32BIT_IDS
feature of KVM_CAP_X2APIC_API capability is enabled.  If it is enabled,
@@ -2992,7 +2992,7 @@ flags:

If KVM_MSI_VALID_DEVID is set, devid contains a unique device identifier
for the device that wrote the MSI message.  For PCI, this is usually a
BFD identifier in the lower 16 bits.
BDF identifier in the lower 16 bits.

On x86, address_hi is ignored unless the KVM_X2APIC_API_USE_32BIT_IDS
feature of KVM_CAP_X2APIC_API capability is enabled.  If it is enabled,
+1 −1
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ Groups:
    KVM_VGIC_V2_ADDR_TYPE_CPU (rw, 64-bit)
      Base address in the guest physical address space of the GIC virtual cpu
      interface register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V2.
      This address needs to be 4K aligned and the region covers 4 KByte.
      This address needs to be 4K aligned and the region covers 8 KByte.

  Errors:

+2 −0
Original line number Diff line number Diff line
@@ -12077,6 +12077,8 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L:	kvmarm@lists.linux.dev
S:	Maintained
T:	git git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git
F:	Documentation/virt/kvm/arm/
F:	Documentation/virt/kvm/devices/arm*
F:	arch/arm64/include/asm/kvm*
F:	arch/arm64/include/uapi/asm/kvm*
F:	arch/arm64/kvm/
+12 −0
Original line number Diff line number Diff line
@@ -152,6 +152,7 @@
#define ESR_ELx_Xs_MASK		(GENMASK_ULL(4, 0))

/* ISS field definitions for exceptions taken in to Hyp */
#define ESR_ELx_FSC_ADDRSZ	(0x00)
#define ESR_ELx_CV		(UL(1) << 24)
#define ESR_ELx_COND_SHIFT	(20)
#define ESR_ELx_COND_MASK	(UL(0xF) << ESR_ELx_COND_SHIFT)
@@ -379,6 +380,11 @@
#ifndef __ASSEMBLY__
#include <asm/types.h>

static inline unsigned long esr_brk_comment(unsigned long esr)
{
	return esr & ESR_ELx_BRK64_ISS_COMMENT_MASK;
}

static inline bool esr_is_data_abort(unsigned long esr)
{
	const unsigned long ec = ESR_ELx_EC(esr);
@@ -386,6 +392,12 @@ static inline bool esr_is_data_abort(unsigned long esr)
	return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR;
}

static inline bool esr_is_cfi_brk(unsigned long esr)
{
	return ESR_ELx_EC(esr) == ESR_ELx_EC_BRK64 &&
	       (esr_brk_comment(esr) & ~CFI_BRK_IMM_MASK) == CFI_BRK_IMM_BASE;
}

static inline bool esr_fsc_is_translation_fault(unsigned long esr)
{
	/* Translation fault, level -1 */
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