Commit 1c67c436 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915/bw: Relocate intel_bw_crtc_min_cdclk() 



intel_bw_crtc_min_cdclk() (aka. the thing that deals with what bspec
calls "Maximum Pipe Read Bandwidth") doesn't really have anything to
do with the rest of intel_bw.c (which is all about SAGV/QGV and
memory bandwidth). Move it into intel_crtc.c (for the lack of a better
place).

And I don't really want to call intel_bw.c functions from intel_crtc.c,
so move out intel_bw_crtc_data_rate() as well. And when we move that we
pretty much have to move intel_bw_crtc_num_active_planes() as well since
the two are meant to be used as a pair (they both implement the same
"ignore the cursor" logic).

And in an effort to keep the namespaces at least semi-sensible we
flip the intel_bw_crtc_ prefix into intel_crtc_bw_.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20251013201236.30084-4-ville.syrjala@linux.intel.com


Reviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
parent 2955b247

drivers/gpu/drm/i915/display/intel_bw.c

+6 −50
Original line number Diff line number Diff line
@@ -827,50 +827,6 @@ void intel_bw_init_hw(struct intel_display *display) 
		icl_get_bw_info(display, dram_info, &icl_sa_info);

}



static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)

{

	/*

	 * We assume cursors are small enough

	 * to not cause bandwidth problems.

	 */

	return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR));

}



static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(crtc_state);

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	unsigned int data_rate = 0;

	enum plane_id plane_id;



	for_each_plane_id_on_crtc(crtc, plane_id) {

		/*

		 * We assume cursors are small enough

		 * to not cause bandwidth problems.

		 */

		if (plane_id == PLANE_CURSOR)

			continue;



		data_rate += crtc_state->data_rate[plane_id];



		if (DISPLAY_VER(display) < 11)

			data_rate += crtc_state->data_rate_y[plane_id];

	}



	return data_rate;

}



/* "Maximum Pipe Read Bandwidth" */

int intel_bw_crtc_min_cdclk(const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(crtc_state);



	if (DISPLAY_VER(display) < 12)

		return 0;



	return DIV_ROUND_UP_ULL(mul_u32_u32(intel_bw_crtc_data_rate(crtc_state), 10), 512);

}



static unsigned int intel_bw_num_active_planes(struct intel_display *display,

					       const struct intel_bw_state *bw_state)

{
@@ -1264,13 +1220,13 @@ static int intel_bw_check_data_rate(struct intel_atomic_state *state, bool *chan 
	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,

					    new_crtc_state, i) {

		unsigned int old_data_rate =

			intel_bw_crtc_data_rate(old_crtc_state);

			intel_crtc_bw_data_rate(old_crtc_state);

		unsigned int new_data_rate =

			intel_bw_crtc_data_rate(new_crtc_state);

			intel_crtc_bw_data_rate(new_crtc_state);

		unsigned int old_active_planes =

			intel_bw_crtc_num_active_planes(old_crtc_state);

			intel_crtc_bw_num_active_planes(old_crtc_state);

		unsigned int new_active_planes =

			intel_bw_crtc_num_active_planes(new_crtc_state);

			intel_crtc_bw_num_active_planes(new_crtc_state);

		struct intel_bw_state *new_bw_state;



		/*
@@ -1426,9 +1382,9 @@ static void intel_bw_crtc_update(struct intel_bw_state *bw_state, 
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);



	bw_state->data_rate[crtc->pipe] =

		intel_bw_crtc_data_rate(crtc_state);

		intel_crtc_bw_data_rate(crtc_state);

	bw_state->num_active_planes[crtc->pipe] =

		intel_bw_crtc_num_active_planes(crtc_state);

		intel_crtc_bw_num_active_planes(crtc_state);



	drm_dbg_kms(display->drm, "pipe %c data rate %u num active planes %u\n",

		    pipe_name(crtc->pipe),

drivers/gpu/drm/i915/display/intel_bw.h

+0 −1
Original line number Diff line number Diff line
@@ -29,7 +29,6 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state); 
void intel_bw_init_hw(struct intel_display *display);

int intel_bw_init(struct intel_display *display);

int intel_bw_atomic_check(struct intel_atomic_state *state);

int intel_bw_crtc_min_cdclk(const struct intel_crtc_state *crtc_state);

void intel_bw_update_hw_state(struct intel_display *display);

void intel_bw_crtc_disable_noatomic(struct intel_crtc *crtc);

drivers/gpu/drm/i915/display/intel_cdclk.c

+1 −2
Original line number Diff line number Diff line
@@ -35,7 +35,6 @@ 
#include "i915_utils.h"

#include "intel_atomic.h"

#include "intel_audio.h"

#include "intel_bw.h"

#include "intel_cdclk.h"

#include "intel_crtc.h"

#include "intel_dbuf_bw.h"
@@ -2842,7 +2841,7 @@ static int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_stat 
		return 0;



	min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);

	min_cdclk = max(min_cdclk, intel_bw_crtc_min_cdclk(crtc_state));

	min_cdclk = max(min_cdclk, intel_crtc_bw_min_cdclk(crtc_state));

	min_cdclk = max(min_cdclk, hsw_ips_min_cdclk(crtc_state));

	min_cdclk = max(min_cdclk, intel_audio_min_cdclk(crtc_state));

	min_cdclk = max(min_cdclk, vlv_dsi_min_cdclk(crtc_state));

drivers/gpu/drm/i915/display/intel_crtc.c

+44 −0
Original line number Diff line number Diff line
@@ -795,3 +795,47 @@ bool intel_any_crtc_active_changed(struct intel_atomic_state *state) 


	return false;

}



unsigned int intel_crtc_bw_num_active_planes(const struct intel_crtc_state *crtc_state)

{

	/*

	 * We assume cursors are small enough

	 * to not cause bandwidth problems.

	 */

	return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR));

}



unsigned int intel_crtc_bw_data_rate(const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(crtc_state);

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	unsigned int data_rate = 0;

	enum plane_id plane_id;



	for_each_plane_id_on_crtc(crtc, plane_id) {

		/*

		 * We assume cursors are small enough

		 * to not cause bandwidth problems.

		 */

		if (plane_id == PLANE_CURSOR)

			continue;



		data_rate += crtc_state->data_rate[plane_id];



		if (DISPLAY_VER(display) < 11)

			data_rate += crtc_state->data_rate_y[plane_id];

	}



	return data_rate;

}



/* "Maximum Pipe Read Bandwidth" */

int intel_crtc_bw_min_cdclk(const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(crtc_state);



	if (DISPLAY_VER(display) < 12)

		return 0;



	return DIV_ROUND_UP_ULL(mul_u32_u32(intel_crtc_bw_data_rate(crtc_state), 10), 512);

}

drivers/gpu/drm/i915/display/intel_crtc.h

+4 −0
Original line number Diff line number Diff line
@@ -65,4 +65,8 @@ bool intel_any_crtc_active_changed(struct intel_atomic_state *state); 
bool intel_crtc_active_changed(const struct intel_crtc_state *old_crtc_state,

			       const struct intel_crtc_state *new_crtc_state);



unsigned int intel_crtc_bw_num_active_planes(const struct intel_crtc_state *crtc_state);

unsigned int intel_crtc_bw_data_rate(const struct intel_crtc_state *crtc_state);

int intel_crtc_bw_min_cdclk(const struct intel_crtc_state *crtc_state);



#endif