Commit 1cea8a28 authored by Josh Poimboeuf's avatar Josh Poimboeuf Committed by Ingo Molnar
Browse files

x86/bugs: Fix BHI handling of RRSBA 



The ARCH_CAP_RRSBA check isn't correct: RRSBA may have already been
disabled by the Spectre v2 mitigation (or can otherwise be disabled by
the BHI mitigation itself if needed).  In that case retpolines are fine.

Fixes: ec9404e4 ("x86/bhi: Add BHI mitigation knob")
Signed-off-by: default avatarJosh Poimboeuf <jpoimboe@kernel.org>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Sean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/6f56f13da34a0834b69163467449be7f58f253dc.1712813475.git.jpoimboe@kernel.org
parent d0485730

arch/x86/kernel/cpu/bugs.c

+18 −12
Original line number Diff line number Diff line
@@ -1538,20 +1538,25 @@ static enum spectre_v2_mitigation __init spectre_v2_select_retpoline(void) 
	return SPECTRE_V2_RETPOLINE;

}



static bool __ro_after_init rrsba_disabled;



/* Disable in-kernel use of non-RSB RET predictors */

static void __init spec_ctrl_disable_kernel_rrsba(void)

{

	u64 x86_arch_cap_msr;

	if (rrsba_disabled)

		return;



	if (!boot_cpu_has(X86_FEATURE_RRSBA_CTRL))

	if (!(x86_arch_cap_msr & ARCH_CAP_RRSBA)) {

		rrsba_disabled = true;

		return;

	}



	x86_arch_cap_msr = x86_read_arch_cap_msr();

	if (!boot_cpu_has(X86_FEATURE_RRSBA_CTRL))

		return;



	if (x86_arch_cap_msr & ARCH_CAP_RRSBA) {

	x86_spec_ctrl_base |= SPEC_CTRL_RRSBA_DIS_S;

	update_spec_ctrl(x86_spec_ctrl_base);

	}

	rrsba_disabled = true;

}



static void __init spectre_v2_determine_rsb_fill_type_at_vmexit(enum spectre_v2_mitigation mode)
@@ -1652,9 +1657,11 @@ static void __init bhi_select_mitigation(void) 
		return;



	/* Retpoline mitigates against BHI unless the CPU has RRSBA behavior */

	if (cpu_feature_enabled(X86_FEATURE_RETPOLINE) &&

	    !(x86_read_arch_cap_msr() & ARCH_CAP_RRSBA))

	if (cpu_feature_enabled(X86_FEATURE_RETPOLINE)) {

		spec_ctrl_disable_kernel_rrsba();

		if (rrsba_disabled)

			return;

	}



	if (spec_ctrl_bhi_dis())

		return;
@@ -2809,8 +2816,7 @@ static const char *spectre_bhi_state(void) 
		return "; BHI: BHI_DIS_S";

	else if  (boot_cpu_has(X86_FEATURE_CLEAR_BHB_LOOP))

		return "; BHI: SW loop, KVM: SW loop";

	else if (boot_cpu_has(X86_FEATURE_RETPOLINE) &&

		 !(x86_arch_cap_msr & ARCH_CAP_RRSBA))

	else if (boot_cpu_has(X86_FEATURE_RETPOLINE) && rrsba_disabled)

		return "; BHI: Retpoline";

	else if  (boot_cpu_has(X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT))

		return "; BHI: Syscall hardening, KVM: SW loop";