Commit 1ced1b8c authored by Nikita Yushchenko's avatar Nikita Yushchenko Committed by Jakub Kicinski
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net: renesas: rswitch: align mdio C45 operations with datasheet 



Per rswitch datasheet, software can know that mdio operation completed
either by polling MPSM.PSME bit, or via interrupt.

Instead, the driver currently polls for interrupt status bit. Although
this still provides correct result, it requires additional register
operations to clean the interrupt status bits, and generally looks wrong.

Fix it to poll MPSM.PSME bit, as the datasheet suggests.

Signed-off-by: default avatarNikita Yushchenko <nikita.yoush@cogentembedded.com>
Reviewed-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://patch.msgid.link/20241216071957.2587354-4-nikita.yoush@cogentembedded.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent da75ba93

drivers/net/ethernet/renesas/rswitch.c

+3 −9
Original line number Diff line number Diff line
@@ -1205,32 +1205,26 @@ static int rswitch_etha_set_access(struct rswitch_etha *etha, bool read, 
	if (devad == 0xffffffff)

		return -ENODEV;



	writel(MMIS1_CLEAR_FLAGS, etha->addr + MMIS1);



	val = MPSM_PSME | MPSM_MFF_C45;

	iowrite32((regad << 16) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM);



	ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS);

	ret = rswitch_reg_wait(etha->addr, MPSM, MPSM_PSME, 0);

	if (ret)

		return ret;



	rswitch_modify(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS);



	if (read) {

		writel((pop << 13) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM);



		ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS);

		ret = rswitch_reg_wait(etha->addr, MPSM, MPSM_PSME, 0);

		if (ret)

			return ret;



		ret = (ioread32(etha->addr + MPSM) & MPSM_PRD_MASK) >> 16;



		rswitch_modify(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS);

	} else {

		iowrite32((data << 16) | (pop << 13) | (devad << 8) | (phyad << 3) | val,

			  etha->addr + MPSM);



		ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PWACS, MMIS1_PWACS);

		ret = rswitch_reg_wait(etha->addr, MPSM, MPSM_PSME, 0);

	}



	return ret;

drivers/net/ethernet/renesas/rswitch.h

+0 −6
Original line number Diff line number Diff line
@@ -743,12 +743,6 @@ enum rswitch_etha_mode { 
#define MPSM_PRD_SHIFT		16

#define MPSM_PRD_MASK		GENMASK(31, MPSM_PRD_SHIFT)



/* Completion flags */

#define MMIS1_PAACS             BIT(2) /* Address */

#define MMIS1_PWACS             BIT(1) /* Write */

#define MMIS1_PRACS             BIT(0) /* Read */

#define MMIS1_CLEAR_FLAGS       0xf



#define MLVC_PLV		BIT(16)



/* GWCA */