Commit 1d6fc048 authored by Rob Herring (Arm)'s avatar Rob Herring (Arm) Committed by Vinod Koul
Browse files

dt-bindings: phy: rockchip: Convert RK3399 PCIe PHY to schema 



Convert the Rockchip RK3399 PCIe PHY to DT schema format. Move the
example to the GRF binding as that has the complete block.

Signed-off-by: default avatarRob Herring (Arm) <robh@kernel.org>
Reviewed-by: default avatarHeiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250415011824.2320039-1-robh@kernel.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent e75d564f

Documentation/devicetree/bindings/phy/rockchip,rk3399-pcie-phy.yaml

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+45 −0
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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/rockchip,rk3399-pcie-phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Rockchip RK3399 PCIE PHY



maintainers:

  - Heiko Stuebner <heiko@sntech.de>



properties:

  compatible:

    const: rockchip,rk3399-pcie-phy



  '#phy-cells':

    oneOf:

      - const: 0

        deprecated: true

      - const: 1

        description: One lane per phy mode



  clocks:

    maxItems: 1



  clock-names:

    const: refclk



  resets:

    maxItems: 1



  reset-names:

    const: phy



required:

  - compatible

  - '#phy-cells'

  - clocks

  - clock-names

  - resets

  - reset-names



additionalProperties: false



...

Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt

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Rockchip PCIE PHY

-----------------------



Required properties:

 - compatible: rockchip,rk3399-pcie-phy

 - clocks: Must contain an entry in clock-names.

	See ../clocks/clock-bindings.txt for details.

 - clock-names: Must be "refclk"

 - resets: Must contain an entry in reset-names.

	See ../reset/reset.txt for details.

 - reset-names: Must be "phy"



Required properties for legacy PHY mode (deprecated):

 - #phy-cells: must be 0



Required properties for per-lane PHY mode (preferred):

 - #phy-cells: must be 1



Example:



grf: syscon@ff770000 {

	compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";

	#address-cells = <1>;

	#size-cells = <1>;



	...



	pcie_phy: pcie-phy {

		compatible = "rockchip,rk3399-pcie-phy";

		#phy-cells = <0>;

		clocks = <&cru SCLK_PCIEPHY_REF>;

		clock-names = "refclk";

		resets = <&cru SRST_PCIEPHY>;

		reset-names = "phy";

	};

};

Documentation/devicetree/bindings/soc/rockchip/grf.yaml

+11 −2
Original line number Diff line number Diff line
@@ -201,8 +201,8 @@ allOf: 


        pcie-phy:

          type: object

          description:

            Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt

          $ref: /schemas/phy/rockchip,rk3399-pcie-phy.yaml#

          unevaluatedProperties: false



      patternProperties:

        "^phy@[0-9a-f]+$":
@@ -326,6 +326,15 @@ examples: 
        #phy-cells = <0>;

      };



      pcie-phy {

        compatible = "rockchip,rk3399-pcie-phy";

        #phy-cells = <1>;

        clocks = <&cru SCLK_PCIEPHY_REF>;

        clock-names = "refclk";

        resets = <&cru SRST_PCIEPHY>;

        reset-names = "phy";

      };



      phy@f780 {

        compatible = "rockchip,rk3399-emmc-phy";

        reg = <0xf780 0x20>;