Commit 1d706875 authored by Paolo Abeni's avatar Paolo Abeni
Browse files

Merge branch 'net-macb-wol-enhancements'

Vineeth Karumanchi says:

====================
net: macb: WOL enhancements

- Add provisioning for queue tie-off and queue disable during suspend.
- Add support for ARP packet types to WoL.
- Advertise WoL attributes by default.
- Extend MACB supported WoL modes to the PHY supported WoL modes.
- Deprecate magic-packet property.

v6: https://lore.kernel.org/netdev/20240617070413.2291511-1-vineeth.karumanchi@amd.com/
v5: https://lore.kernel.org/netdev/20240611162827.887162-1-vineeth.karumanchi@amd.com/
v4: https://lore.kernel.org/lkml/20240610053936.622237-1-vineeth.karumanchi@amd.com/
v3: https://lore.kernel.org/netdev/20240605102457.4050539-1-vineeth.karumanchi@amd.com/
v2: https://lore.kernel.org/netdev/20240222153848.2374782-1-vineeth.karumanchi@amd.com/
v1: https://lore.kernel.org/lkml/20240130104845.3995341-1-vineeth.karumanchi@amd.com/#t
====================

Link: https://lore.kernel.org/r/20240621045735.3031357-1-vineeth.karumanchi@amd.com


Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parents 7e7c714a 783bfe27
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+1 −0
Original line number Diff line number Diff line
@@ -146,6 +146,7 @@ patternProperties:

      magic-packet:
        type: boolean
        deprecated: true
        description:
          Indicates that the hardware supports waking up via magic packet.

+8 −0
Original line number Diff line number Diff line
@@ -645,6 +645,10 @@
#define GEM_T2OFST_OFFSET			0 /* offset value */
#define GEM_T2OFST_SIZE				7

/* Bitfields in queue pointer registers */
#define MACB_QUEUE_DISABLE_OFFSET		0 /* disable queue */
#define MACB_QUEUE_DISABLE_SIZE			1

/* Offset for screener type 2 compare values (T2CMPOFST).
 * Note the offset is applied after the specified point,
 * e.g. GEM_T2COMPOFST_ETYPE denotes the EtherType field, so an offset
@@ -733,6 +737,7 @@
#define MACB_CAPS_NEEDS_RSTONUBR		0x00000100
#define MACB_CAPS_MIIONRGMII			0x00000200
#define MACB_CAPS_NEED_TSUCLK			0x00000400
#define MACB_CAPS_QUEUE_DISABLE			0x00000800
#define MACB_CAPS_PCS				0x01000000
#define MACB_CAPS_HIGH_SPEED			0x02000000
#define MACB_CAPS_CLK_HW_CHG			0x04000000
@@ -1254,6 +1259,8 @@ struct macb {
	u32	(*macb_reg_readl)(struct macb *bp, int offset);
	void	(*macb_reg_writel)(struct macb *bp, int offset, u32 value);

	struct macb_dma_desc	*rx_ring_tieoff;
	dma_addr_t		rx_ring_tieoff_dma;
	size_t			rx_buffer_size;

	unsigned int		rx_ring_size;
@@ -1299,6 +1306,7 @@ struct macb {
	unsigned int		jumbo_max_len;

	u32			wol;
	u32			wolopts;

	/* holds value of rx watermark value for pbuf_rxcutthru register */
	u32			rx_watermark;
+91 −30
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@
#include <linux/ptp_classify.h>
#include <linux/reset.h>
#include <linux/firmware/xlnx-zynqmp.h>
#include <linux/inetdevice.h>
#include "macb.h"

/* This structure is only used for MACB on SiFive FU540 devices */
@@ -84,8 +85,7 @@ struct sifive_fu540_macb_mgmt {
#define GEM_MTU_MIN_SIZE	ETH_MIN_MTU
#define MACB_NETIF_LSO		NETIF_F_TSO

#define MACB_WOL_HAS_MAGIC_PACKET	(0x1 << 0)
#define MACB_WOL_ENABLED		(0x1 << 1)
#define MACB_WOL_ENABLED		BIT(0)

#define HS_SPEED_10000M			4
#define MACB_SERDES_RATE_10G		1
@@ -2477,6 +2477,12 @@ static void macb_free_consistent(struct macb *bp)
	unsigned int q;
	int size;

	if (bp->rx_ring_tieoff) {
		dma_free_coherent(&bp->pdev->dev, macb_dma_desc_get_size(bp),
				  bp->rx_ring_tieoff, bp->rx_ring_tieoff_dma);
		bp->rx_ring_tieoff = NULL;
	}

	bp->macbgem_ops.mog_free_rx_buffers(bp);

	for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
@@ -2568,6 +2574,16 @@ static int macb_alloc_consistent(struct macb *bp)
	if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
		goto out_err;

	/* Required for tie off descriptor for PM cases */
	if (!(bp->caps & MACB_CAPS_QUEUE_DISABLE)) {
		bp->rx_ring_tieoff = dma_alloc_coherent(&bp->pdev->dev,
							macb_dma_desc_get_size(bp),
							&bp->rx_ring_tieoff_dma,
							GFP_KERNEL);
		if (!bp->rx_ring_tieoff)
			goto out_err;
	}

	return 0;

out_err:
@@ -2575,6 +2591,19 @@ static int macb_alloc_consistent(struct macb *bp)
	return -ENOMEM;
}

static void macb_init_tieoff(struct macb *bp)
{
	struct macb_dma_desc *desc = bp->rx_ring_tieoff;

	if (bp->caps & MACB_CAPS_QUEUE_DISABLE)
		return;
	/* Setup a wrapping descriptor with no free slots
	 * (WRAP and USED) to tie off/disable unused RX queues.
	 */
	macb_set_addr(bp, desc, MACB_BIT(RX_WRAP) | MACB_BIT(RX_USED));
	desc->ctrl = 0;
}

static void gem_init_rings(struct macb *bp)
{
	struct macb_queue *queue;
@@ -2598,6 +2627,7 @@ static void gem_init_rings(struct macb *bp)
		gem_rx_refill(queue);
	}

	macb_init_tieoff(bp);
}

static void macb_init_rings(struct macb *bp)
@@ -2615,6 +2645,8 @@ static void macb_init_rings(struct macb *bp)
	bp->queues[0].tx_head = 0;
	bp->queues[0].tx_tail = 0;
	desc->ctrl |= MACB_BIT(TX_WRAP);

	macb_init_tieoff(bp);
}

static void macb_reset_hw(struct macb *bp)
@@ -3246,13 +3278,11 @@ static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
{
	struct macb *bp = netdev_priv(netdev);

	if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
	phylink_ethtool_get_wol(bp->phylink, wol);
		wol->supported |= WAKE_MAGIC;
	wol->supported |= (WAKE_MAGIC | WAKE_ARP);

		if (bp->wol & MACB_WOL_ENABLED)
			wol->wolopts |= WAKE_MAGIC;
	}
	/* Add macb wolopts to phy wolopts */
	wol->wolopts |= bp->wolopts;
}

static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
@@ -3262,22 +3292,15 @@ static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)

	/* Pass the order to phylink layer */
	ret = phylink_ethtool_set_wol(bp->phylink, wol);
	/* Don't manage WoL on MAC if handled by the PHY
	 * or if there's a failure in talking to the PHY
	 */
	if (!ret || ret != -EOPNOTSUPP)
	/* Don't manage WoL on MAC, if PHY set_wol() fails */
	if (ret && ret != -EOPNOTSUPP)
		return ret;

	if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
	    (wol->wolopts & ~WAKE_MAGIC))
		return -EOPNOTSUPP;

	if (wol->wolopts & WAKE_MAGIC)
		bp->wol |= MACB_WOL_ENABLED;
	else
		bp->wol &= ~MACB_WOL_ENABLED;
	bp->wolopts = (wol->wolopts & WAKE_MAGIC) ? WAKE_MAGIC : 0;
	bp->wolopts |= (wol->wolopts & WAKE_ARP) ? WAKE_ARP : 0;
	bp->wol = (wol->wolopts) ? MACB_WOL_ENABLED : 0;

	device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
	device_set_wakeup_enable(&bp->pdev->dev, bp->wol);

	return 0;
}
@@ -4917,7 +4940,8 @@ static const struct macb_config sama7g5_emac_config = {

static const struct macb_config versal_config = {
	.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
		MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH | MACB_CAPS_NEED_TSUCLK,
		MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH | MACB_CAPS_NEED_TSUCLK |
		MACB_CAPS_QUEUE_DISABLE,
	.dma_burst_length = 16,
	.clk_init = macb_clk_init,
	.init = init_reset_optional,
@@ -5053,9 +5077,7 @@ static int macb_probe(struct platform_device *pdev)
		bp->max_tx_length = GEM_MAX_TX_LEN;

	bp->wol = 0;
	if (of_property_read_bool(np, "magic-packet"))
		bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
	device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
	device_set_wakeup_capable(&pdev->dev, 1);

	bp->usrio = macb_config->usrio;

@@ -5211,10 +5233,13 @@ static int __maybe_unused macb_suspend(struct device *dev)
{
	struct net_device *netdev = dev_get_drvdata(dev);
	struct macb *bp = netdev_priv(netdev);
	struct in_ifaddr *ifa = NULL;
	struct macb_queue *queue;
	struct in_device *idev;
	unsigned long flags;
	unsigned int q;
	int err;
	u32 tmp;

	if (!device_may_wakeup(&bp->dev->dev))
		phy_exit(bp->sgmii_phy);
@@ -5223,18 +5248,54 @@ static int __maybe_unused macb_suspend(struct device *dev)
		return 0;

	if (bp->wol & MACB_WOL_ENABLED) {
		/* Check for IP address in WOL ARP mode */
		idev = __in_dev_get_rcu(bp->dev);
		if (idev && idev->ifa_list)
			ifa = rcu_access_pointer(idev->ifa_list);
		if ((bp->wolopts & WAKE_ARP) && !ifa) {
			netdev_err(netdev, "IP address not assigned as required by WoL walk ARP\n");
			return -EOPNOTSUPP;
		}
		spin_lock_irqsave(&bp->lock, flags);
		/* Flush all status bits */
		macb_writel(bp, TSR, -1);
		macb_writel(bp, RSR, -1);

		/* Disable Tx and Rx engines before  disabling the queues,
		 * this is mandatory as per the IP spec sheet
		 */
		tmp = macb_readl(bp, NCR);
		macb_writel(bp, NCR, tmp & ~(MACB_BIT(TE) | MACB_BIT(RE)));
		for (q = 0, queue = bp->queues; q < bp->num_queues;
		     ++q, ++queue) {
			/* Disable RX queues */
			if (bp->caps & MACB_CAPS_QUEUE_DISABLE) {
				queue_writel(queue, RBQP, MACB_BIT(QUEUE_DISABLE));
			} else {
				/* Tie off RX queues */
				queue_writel(queue, RBQP,
					     lower_32_bits(bp->rx_ring_tieoff_dma));
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
				queue_writel(queue, RBQPH,
					     upper_32_bits(bp->rx_ring_tieoff_dma));
#endif
			}
			/* Disable all interrupts */
			queue_writel(queue, IDR, -1);
			queue_readl(queue, ISR);
			if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
				queue_writel(queue, ISR, -1);
		}
		/* Enable Receive engine */
		macb_writel(bp, NCR, tmp | MACB_BIT(RE));
		/* Flush all status bits */
		macb_writel(bp, TSR, -1);
		macb_writel(bp, RSR, -1);

		tmp = (bp->wolopts & WAKE_MAGIC) ? MACB_BIT(MAG) : 0;
		if (bp->wolopts & WAKE_ARP) {
			tmp |= MACB_BIT(ARP);
			/* write IP address into register */
			tmp |= MACB_BFEXT(IP, be32_to_cpu(ifa->ifa_local));
		}

		/* Change interrupt handler and
		 * Enable WoL IRQ on queue 0
		 */
@@ -5250,7 +5311,7 @@ static int __maybe_unused macb_suspend(struct device *dev)
				return err;
			}
			queue_writel(bp->queues, IER, GEM_BIT(WOL));
			gem_writel(bp, WOL, MACB_BIT(MAG));
			gem_writel(bp, WOL, tmp);
		} else {
			err = devm_request_irq(dev, bp->queues[0].irq, macb_wol_interrupt,
					       IRQF_SHARED, netdev->name, bp->queues);
@@ -5262,7 +5323,7 @@ static int __maybe_unused macb_suspend(struct device *dev)
				return err;
			}
			queue_writel(bp->queues, IER, MACB_BIT(WOL));
			macb_writel(bp, WOL, MACB_BIT(MAG));
			macb_writel(bp, WOL, tmp);
		}
		spin_unlock_irqrestore(&bp->lock, flags);