Commit 1d8fdabe authored by Michael Hennerich's avatar Michael Hennerich Committed by Jonathan Cameron
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iio: frequency: adf4350: Fix ADF4350_REG3_12BIT_CLKDIV_MODE 



The clk div bits (2 bits wide) do not start in bit 16 but in bit 15. Fix it
accordingly.

Fixes: e31166f0 ("iio: frequency: New driver for Analog Devices ADF4350/ADF4351 Wideband Synthesizers")
Signed-off-by: default avatarMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: default avatarNuno Sá <nuno.sa@analog.com>
Link: https://patch.msgid.link/20250829-adf4350-fix-v2-2-0bf543ba797d@analog.com


Cc: <Stable@vger.kernel.org>
Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
parent 33d7ecbf

include/linux/iio/frequency/adf4350.h

+1 −1
Original line number Diff line number Diff line
@@ -51,7 +51,7 @@ 


/* REG3 Bit Definitions */

#define ADF4350_REG3_12BIT_CLKDIV(x)		((x) << 3)

#define ADF4350_REG3_12BIT_CLKDIV_MODE(x)	((x) << 16)

#define ADF4350_REG3_12BIT_CLKDIV_MODE(x)	((x) << 15)

#define ADF4350_REG3_12BIT_CSR_EN		(1 << 18)

#define ADF4351_REG3_CHARGE_CANCELLATION_EN	(1 << 21)

#define ADF4351_REG3_ANTI_BACKLASH_3ns_EN	(1 << 22)