Unverified Commit 1db4d0ed authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'qcom-clk-for-7.1' of... 

Merge tag 'qcom-clk-for-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom

Pull Qualcomm clock driver updates from Bjorn Andersson:

 - Global TCSR, RPMh, and display clock controller support for
   the Qualcomm Eliza platform
 - TCSR, the multiple global, and the RPMh clock controller
   support for the Qualcomm Nord platform
 - GPU clock controller support for Qualcomm SM8750
 - Video and GPU clock controller support for Qualcomm Glymur
 - Global clock controller support for Qualcomm IPQ5210
 - Introduce various smaller display-related fixes across
   Qualcomm Kaanapali, Milos, SC8280XP, SM4450, SM8250, and
   SA8775P.
 - Add missing GDSCs and fix retention flags for PCIe and USB
   power domains on SC8180X.
 - Enable runtime PM support to ensure performance votes are
   propagated to CX on Qualcomm platforms.
 - Mark the USB QTB clock as always-on on Qualcomm Hamoa, in
   order to ensure the SMMU can work even when USB controller
   device is sleeping.
 - Qualcomm IPQ6018 and IPQ8074 support in the IPQ CMN PLL
   driver
 - MDSS resets for Qualcomm SC7180, SM6115, and SM6125, to allow
   display subsystem driver to reset the hardware from the state
   left by the bootloader.

* tag 'qcom-clk-for-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (67 commits)
  clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC
  clk: qcom: rpmh: Add support for Nord rpmh clocks
  clk: qcom: Add TCSR clock driver for Nord SoC
  dt-bindings: clock: qcom: Add Nord Global Clock Controller
  dt-bindings: clock: qcom-rpmhcc: Add support for Nord SoCs
  dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller
  clk: qcom: gcc-x1e80100: Keep GCC USB QTB clock always ON
  clk: qcom: Constify list of critical CBCR registers
  clk: qcom: Constify qcom_cc_driver_data
  clk: qcom: videocc-glymur: Constify qcom_cc_desc
  clk: qcom: Add a driver for SM8750 GPU clocks
  dt-bindings: clock: qcom: Add SM8750 GPU clocks
  clk: qcom: ipq-cmn-pll: Add IPQ8074 SoC support
  dt-bindings: clock: qcom: Add CMN PLL support for IPQ8074
  clk: qcom: ipq-cmn-pll: Add IPQ6018 SoC support
  dt-bindings: clock: qcom: Add CMN PLL support for IPQ6018
  clk: qcom: gdsc: Fix error path on registration of multiple pm subdomains
  dt-bindings: clock: qcom: Add missing power-domains property
  clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock
  clk: qcom: dispcc-sc7180: Add missing MDSS resets
  ...
parents c3692998 a4f780cd

Documentation/devicetree/bindings/clock/qcom,eliza-dispcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,eliza-dispcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Display Clock & Reset Controller for Qualcomm Eliza SoC



maintainers:

  - Bjorn Andersson <andersson@kernel.org>

  - Konrad Dybcio <konradybcio@kernel.org>

  - Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>



description: |

  Display clock control module provides the clocks, resets and power

  domains on Qualcomm Eliza SoC platform.



  See also:

  - include/dt-bindings/clock/qcom,eliza-dispcc.h



properties:

  compatible:

    enum:

      - qcom,eliza-dispcc



  clocks:

    items:

      - description: Board XO source

      - description: Board Always On XO source

      - description: Display's AHB clock

      - description: sleep clock

      - description: Byte clock from DSI PHY0

      - description: Pixel clock from DSI PHY0

      - description: Byte clock from DSI PHY1

      - description: Pixel clock from DSI PHY1

      - description: Link clock from DP PHY0

      - description: VCO DIV clock from DP PHY0

      - description: Link clock from DP PHY1

      - description: VCO DIV clock from DP PHY1

      - description: Link clock from DP PHY2

      - description: VCO DIV clock from DP PHY2

      - description: Link clock from DP PHY3

      - description: VCO DIV clock from DP PHY3

      - description: HDMI link clock from HDMI PHY



  power-domains:

    maxItems: 1



  required-opps:

    maxItems: 1



required:

  - compatible

  - clocks

  - '#power-domain-cells'



allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>

    #include <dt-bindings/clock/qcom,eliza-gcc.h>

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/power/qcom,rpmhpd.h>

    clock-controller@af00000 {

        compatible = "qcom,eliza-dispcc";

        reg = <0x0af00000 0x20000>;

        clocks = <&bi_tcxo_div2>,

                 <&bi_tcxo_ao_div2>,

                 <&gcc GCC_DISP_AHB_CLK>,

                 <&sleep_clk>,

                 <&dsi0_phy DSI_BYTE_PLL_CLK>,

                 <&dsi0_phy DSI_PIXEL_PLL_CLK>,

                 <&dsi1_phy DSI_BYTE_PLL_CLK>,

                 <&dsi1_phy DSI_PIXEL_PLL_CLK>,

                 <&dp0_phy 0>,

                 <&dp0_phy 1>,

                 <&dp1_phy 0>,

                 <&dp1_phy 1>,

                 <&dp2_phy 0>,

                 <&dp2_phy 1>,

                 <&dp3_phy 0>,

                 <&dp3_phy 1>,

                 <&hdmi_phy>;



        #clock-cells = <1>;

        #power-domain-cells = <1>;

        #reset-cells = <1>;



        power-domains = <&rpmhpd RPMHPD_MMCX>;

        required-opps = <&rpmhpd_opp_low_svs>;

    };

...

Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml

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@@ -4,14 +4,14 @@ 
$id: http://devicetree.org/schemas/clock/qcom,glymur-dispcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Display Clock & Reset Controller on GLYMUR

title: Qualcomm Display Clock & Reset Controller on Glymur SoC



maintainers:

  - Taniya Das <taniya.das@oss.qualcomm.com>



description: |

  Qualcomm display clock control module which supports the clocks, resets and

  power domains for the MDSS instances on GLYMUR SoC.

  power domains for the MDSS instances on Glymur SoC.



  See also:

    include/dt-bindings/clock/qcom,dispcc-glymur.h

Documentation/devicetree/bindings/clock/qcom,ipq5210-gcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,ipq5210-gcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller on IPQ5210



maintainers:

  - Bjorn Andersson <andersson@kernel.org>

  - Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>



description: |

  Qualcomm global clock control module provides the clocks, resets and power

  domains on IPQ5210



  See also:

    include/dt-bindings/clock/qcom,ipq5210-gcc.h

    include/dt-bindings/reset/qcom,ipq5210-gcc.h



properties:

  compatible:

    const: qcom,ipq5210-gcc



  clocks:

    items:

      - description: Board XO source

      - description: Sleep clock source

      - description: PCIE30 PHY0 pipe clock source

      - description: PCIE30 PHY1 pipe clock source

      - description: USB3 PHY pipe clock source

      - description: NSS common clock source



  '#power-domain-cells': false



  '#interconnect-cells':

    const: 1



required:

  - compatible

  - clocks



allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |

    clock-controller@1800000 {

      compatible = "qcom,ipq5210-gcc";

      reg = <0x01800000 0x40000>;

      clocks = <&xo_board_clk>,

               <&sleep_clk>,

               <&pcie30_phy0_pipe_clk>,

               <&pcie30_phy1_pipe_clk>,

               <&usb3phy_0_cc_pipe_clk>,

               <&nss_cmn_clk>;

      #clock-cells = <1>;

      #reset-cells = <1>;

    };

...

Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml

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@@ -26,6 +26,8 @@ properties: 
    enum:

      - qcom,ipq5018-cmn-pll

      - qcom,ipq5424-cmn-pll

      - qcom,ipq6018-cmn-pll

      - qcom,ipq8074-cmn-pll

      - qcom,ipq9574-cmn-pll



  reg:

Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml

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@@ -20,7 +20,9 @@ description: | 
properties:

  compatible:

    enum:

      - qcom,glymur-gxclkctl

      - qcom,kaanapali-gxclkctl

      - qcom,sm8750-gxclkctl



  power-domains:

    description: