Commit 1dd1bf50 authored by Russell King (Oracle)'s avatar Russell King (Oracle) Committed by Jakub Kicinski
Browse files

net: xpcs: rearrange register definitions 



Place register number definitions immediately above their field
definitions and order by register number.

Signed-off-by: default avatarRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/E1tjblS-00448F-8v@rmk-PC.armlinux.org.uk


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 0784d83d

drivers/net/pcs/pcs-xpcs.h

+8 −17
Original line number Diff line number Diff line
@@ -55,23 +55,11 @@ 
/* Clause 37 Defines */

/* VR MII MMD registers offsets */

#define DW_VR_MII_DIG_CTRL1		0x8000

#define DW_VR_MII_AN_CTRL		0x8001

#define DW_VR_MII_AN_INTR_STS		0x8002

/* EEE Mode Control Register */

#define DW_VR_MII_EEE_MCTRL0		0x8006

#define DW_VR_MII_EEE_MCTRL1		0x800b

#define DW_VR_MII_DIG_CTRL2		0x80e1



/* VR_MII_DIG_CTRL1 */

#define DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW		BIT(9)

#define DW_VR_MII_DIG_CTRL1_2G5_EN		BIT(2)

#define DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL	BIT(0)



/* VR_MII_DIG_CTRL2 */

#define DW_VR_MII_DIG_CTRL2_TX_POL_INV		BIT(4)

#define DW_VR_MII_DIG_CTRL2_RX_POL_INV		BIT(0)



/* VR_MII_AN_CTRL */

#define DW_VR_MII_AN_CTRL		0x8001

#define DW_VR_MII_AN_CTRL_8BIT			BIT(8)

#define DW_VR_MII_TX_CONFIG_MASK		BIT(3)

#define DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII	0x1
@@ -81,7 +69,7 @@ 
#define DW_VR_MII_PCS_MODE_C37_SGMII		0x2

#define DW_VR_MII_AN_INTR_EN			BIT(0)



/* VR_MII_AN_INTR_STS */

#define DW_VR_MII_AN_INTR_STS		0x8002

#define DW_VR_MII_AN_STS_C37_ANCMPLT_INTR	BIT(0)

#define DW_VR_MII_AN_STS_C37_ANSGM_FD		BIT(1)

#define DW_VR_MII_AN_STS_C37_ANSGM_SP		GENMASK(3, 2)
@@ -90,19 +78,22 @@ 
#define DW_VR_MII_C37_ANSGM_SP_1000		0x2

#define DW_VR_MII_C37_ANSGM_SP_LNKSTS		BIT(4)



/* VR MII EEE Control 0 defines */

#define DW_VR_MII_EEE_MCTRL0		0x8006

#define DW_VR_MII_EEE_LTX_EN			BIT(0)  /* LPI Tx Enable */

#define DW_VR_MII_EEE_LRX_EN			BIT(1)  /* LPI Rx Enable */

#define DW_VR_MII_EEE_TX_QUIET_EN		BIT(2)  /* Tx Quiet Enable */

#define DW_VR_MII_EEE_RX_QUIET_EN		BIT(3)  /* Rx Quiet Enable */

#define DW_VR_MII_EEE_TX_EN_CTRL		BIT(4)  /* Tx Control Enable */

#define DW_VR_MII_EEE_RX_EN_CTRL		BIT(7)  /* Rx Control Enable */



#define DW_VR_MII_EEE_MULT_FACT_100NS		GENMASK(11, 8)



/* VR MII EEE Control 1 defines */

#define DW_VR_MII_EEE_MCTRL1		0x800b

#define DW_VR_MII_EEE_TRN_LPI		BIT(0)	/* Transparent Mode Enable */



#define DW_VR_MII_DIG_CTRL2		0x80e1

#define DW_VR_MII_DIG_CTRL2_TX_POL_INV		BIT(4)

#define DW_VR_MII_DIG_CTRL2_RX_POL_INV		BIT(0)



#define DW_XPCS_INFO_DECLARE(_name, _pcs, _pma)				\

	static const struct dw_xpcs_info _name = { .pcs = _pcs, .pma = _pma }