Commit 1dd3e8a8 authored by Tiezhu Yang's avatar Tiezhu Yang Committed by Huacai Chen
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LoongArch: Define instruction formats for AM{SWAP/ADD}.{B/H} and DBAR 



The 8 and 16 bit read-modify-write atomic instructions amadd.{b/h} and
amswap.{b/h} were newly added in the latest LoongArch Reference Manual,
define the instruction format and check whether support via CPUCFG.

Furthermore, define the instruction format for DBAR which will be used
to support BPF load-acquire and store-release instructions.

This is preparation for later patches.

Acked-by: default avatarHengqi Chen <hengqi.chen@gmail.com>
Signed-off-by: default avatarTiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
parent 2c749f73

arch/loongarch/include/asm/cpu-features.h

+1 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ 
 */

#define cpu_has_cpucfg		cpu_opt(LOONGARCH_CPU_CPUCFG)

#define cpu_has_lam		cpu_opt(LOONGARCH_CPU_LAM)

#define cpu_has_lam_bh		cpu_opt(LOONGARCH_CPU_LAM_BH)

#define cpu_has_scq		cpu_opt(LOONGARCH_CPU_SCQ)

#define cpu_has_ual		cpu_opt(LOONGARCH_CPU_UAL)

#define cpu_has_fpu		cpu_opt(LOONGARCH_CPU_FPU)

arch/loongarch/include/asm/cpu.h

+33 −31
Original line number Diff line number Diff line
@@ -95,40 +95,42 @@ static inline char *id_to_core_name(unsigned int id) 
 */

#define CPU_FEATURE_CPUCFG		0	/* CPU has CPUCFG */

#define CPU_FEATURE_LAM			1	/* CPU has Atomic instructions */

#define CPU_FEATURE_SCQ			2	/* CPU has SC.Q instruction */

#define CPU_FEATURE_UAL			3	/* CPU supports unaligned access */

#define CPU_FEATURE_FPU			4	/* CPU has FPU */

#define CPU_FEATURE_LSX			5	/* CPU has LSX (128-bit SIMD) */

#define CPU_FEATURE_LASX		6	/* CPU has LASX (256-bit SIMD) */

#define CPU_FEATURE_CRC32		7	/* CPU has CRC32 instructions */

#define CPU_FEATURE_COMPLEX		8	/* CPU has Complex instructions */

#define CPU_FEATURE_CRYPTO		9	/* CPU has Crypto instructions */

#define CPU_FEATURE_LVZ			10	/* CPU has Virtualization extension */

#define CPU_FEATURE_LBT_X86		11	/* CPU has X86 Binary Translation */

#define CPU_FEATURE_LBT_ARM		12	/* CPU has ARM Binary Translation */

#define CPU_FEATURE_LBT_MIPS		13	/* CPU has MIPS Binary Translation */

#define CPU_FEATURE_TLB			14	/* CPU has TLB */

#define CPU_FEATURE_CSR			15	/* CPU has CSR */

#define CPU_FEATURE_IOCSR		16	/* CPU has IOCSR */

#define CPU_FEATURE_WATCH		17	/* CPU has watchpoint registers */

#define CPU_FEATURE_VINT		18	/* CPU has vectored interrupts */

#define CPU_FEATURE_CSRIPI		19	/* CPU has CSR-IPI */

#define CPU_FEATURE_EXTIOI		20	/* CPU has EXT-IOI */

#define CPU_FEATURE_PREFETCH		21	/* CPU has prefetch instructions */

#define CPU_FEATURE_PMP			22	/* CPU has perfermance counter */

#define CPU_FEATURE_SCALEFREQ		23	/* CPU supports cpufreq scaling */

#define CPU_FEATURE_FLATMODE		24	/* CPU has flat mode */

#define CPU_FEATURE_EIODECODE		25	/* CPU has EXTIOI interrupt pin decode mode */

#define CPU_FEATURE_GUESTID		26	/* CPU has GuestID feature */

#define CPU_FEATURE_HYPERVISOR		27	/* CPU has hypervisor (running in VM) */

#define CPU_FEATURE_PTW			28	/* CPU has hardware page table walker */

#define CPU_FEATURE_LSPW		29	/* CPU has LSPW (lddir/ldpte instructions) */

#define CPU_FEATURE_MSGINT		30	/* CPU has MSG interrupt */

#define CPU_FEATURE_AVECINT		31	/* CPU has AVEC interrupt */

#define CPU_FEATURE_REDIRECTINT		32	/* CPU has interrupt remapping */

#define CPU_FEATURE_LAM_BH		2	/* CPU has AM{SWAP/ADD}[_DB].{B/H} instructions */

#define CPU_FEATURE_SCQ			3	/* CPU has SC.Q instruction */

#define CPU_FEATURE_UAL			4	/* CPU supports unaligned access */

#define CPU_FEATURE_FPU			5	/* CPU has FPU */

#define CPU_FEATURE_LSX			6	/* CPU has LSX (128-bit SIMD) */

#define CPU_FEATURE_LASX		7	/* CPU has LASX (256-bit SIMD) */

#define CPU_FEATURE_CRC32		8	/* CPU has CRC32 instructions */

#define CPU_FEATURE_COMPLEX		9	/* CPU has Complex instructions */

#define CPU_FEATURE_CRYPTO		10	/* CPU has Crypto instructions */

#define CPU_FEATURE_LVZ			11	/* CPU has Virtualization extension */

#define CPU_FEATURE_LBT_X86		12	/* CPU has X86 Binary Translation */

#define CPU_FEATURE_LBT_ARM		13	/* CPU has ARM Binary Translation */

#define CPU_FEATURE_LBT_MIPS		14	/* CPU has MIPS Binary Translation */

#define CPU_FEATURE_TLB			15	/* CPU has TLB */

#define CPU_FEATURE_CSR			16	/* CPU has CSR */

#define CPU_FEATURE_IOCSR		17	/* CPU has IOCSR */

#define CPU_FEATURE_WATCH		18	/* CPU has watchpoint registers */

#define CPU_FEATURE_VINT		19	/* CPU has vectored interrupts */

#define CPU_FEATURE_CSRIPI		20	/* CPU has CSR-IPI */

#define CPU_FEATURE_EXTIOI		21	/* CPU has EXT-IOI */

#define CPU_FEATURE_PREFETCH		22	/* CPU has prefetch instructions */

#define CPU_FEATURE_PMP			23	/* CPU has perfermance counter */

#define CPU_FEATURE_SCALEFREQ		24	/* CPU supports cpufreq scaling */

#define CPU_FEATURE_FLATMODE		25	/* CPU has flat mode */

#define CPU_FEATURE_EIODECODE		26	/* CPU has EXTIOI interrupt pin decode mode */

#define CPU_FEATURE_GUESTID		27	/* CPU has GuestID feature */

#define CPU_FEATURE_HYPERVISOR		28	/* CPU has hypervisor (running in VM) */

#define CPU_FEATURE_PTW			29	/* CPU has hardware page table walker */

#define CPU_FEATURE_LSPW		30	/* CPU has LSPW (lddir/ldpte instructions) */

#define CPU_FEATURE_MSGINT		31	/* CPU has MSG interrupt */

#define CPU_FEATURE_AVECINT		32	/* CPU has AVEC interrupt */

#define CPU_FEATURE_REDIRECTINT		33	/* CPU has interrupt remapping */



#define LOONGARCH_CPU_CPUCFG		BIT_ULL(CPU_FEATURE_CPUCFG)

#define LOONGARCH_CPU_LAM		BIT_ULL(CPU_FEATURE_LAM)

#define LOONGARCH_CPU_LAM_BH		BIT_ULL(CPU_FEATURE_LAM_BH)

#define LOONGARCH_CPU_SCQ		BIT_ULL(CPU_FEATURE_SCQ)

#define LOONGARCH_CPU_UAL		BIT_ULL(CPU_FEATURE_UAL)

#define LOONGARCH_CPU_FPU		BIT_ULL(CPU_FEATURE_FPU)

arch/loongarch/include/asm/inst.h

+10 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ 


enum reg0i15_op {

	break_op	= 0x54,

	dbar_op		= 0x70e4,

};



enum reg0i26_op {
@@ -194,6 +195,10 @@ enum reg3_op { 
	fstxs_op	= 0x7070,

	fstxd_op	= 0x7078,

	scq_op		= 0x70ae,

	amswapb_op	= 0x70b8,

	amswaph_op	= 0x70b9,

	amaddb_op	= 0x70ba,

	amaddh_op	= 0x70bb,

	amswapw_op	= 0x70c0,

	amswapd_op	= 0x70c1,

	amaddw_op	= 0x70c2,
@@ -543,6 +548,7 @@ static inline void emit_##NAME(union loongarch_instruction *insn, \ 
}



DEF_EMIT_REG0I15_FORMAT(break, break_op)

DEF_EMIT_REG0I15_FORMAT(dbar, dbar_op)



/* like emit_break(imm) but returns a constant expression */

#define __emit_break(imm)	((u32)((imm) | (break_op << 15)))
@@ -763,6 +769,8 @@ DEF_EMIT_REG3_FORMAT(stxb, stxb_op) 
DEF_EMIT_REG3_FORMAT(stxh, stxh_op)

DEF_EMIT_REG3_FORMAT(stxw, stxw_op)

DEF_EMIT_REG3_FORMAT(stxd, stxd_op)

DEF_EMIT_REG3_FORMAT(amaddb, amaddb_op)

DEF_EMIT_REG3_FORMAT(amaddh, amaddh_op)

DEF_EMIT_REG3_FORMAT(amaddw, amaddw_op)

DEF_EMIT_REG3_FORMAT(amaddd, amaddd_op)

DEF_EMIT_REG3_FORMAT(amandw, amandw_op)
@@ -771,6 +779,8 @@ DEF_EMIT_REG3_FORMAT(amorw, amorw_op) 
DEF_EMIT_REG3_FORMAT(amord, amord_op)

DEF_EMIT_REG3_FORMAT(amxorw, amxorw_op)

DEF_EMIT_REG3_FORMAT(amxord, amxord_op)

DEF_EMIT_REG3_FORMAT(amswapb, amswapb_op)

DEF_EMIT_REG3_FORMAT(amswaph, amswaph_op)

DEF_EMIT_REG3_FORMAT(amswapw, amswapw_op)

DEF_EMIT_REG3_FORMAT(amswapd, amswapd_op)

arch/loongarch/include/uapi/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -19,5 +19,6 @@ 
#define HWCAP_LOONGARCH_PTW		(1 << 13)

#define HWCAP_LOONGARCH_LSPW		(1 << 14)

#define HWCAP_LOONGARCH_SCQ		(1 << 15)

#define HWCAP_LOONGARCH_LAM_BH		(1 << 16)



#endif /* _UAPI_ASM_HWCAP_H */

arch/loongarch/kernel/cpu-probe.c

+4 −0
Original line number Diff line number Diff line
@@ -178,6 +178,10 @@ static void cpu_probe_common(struct cpuinfo_loongarch *c) 
		c->options |= LOONGARCH_CPU_LAM;

		elf_hwcap |= HWCAP_LOONGARCH_LAM;

	}

	if (config & CPUCFG2_LAM_BH) {

		c->options |= LOONGARCH_CPU_LAM_BH;

		elf_hwcap |= HWCAP_LOONGARCH_LAM_BH;

	}

	if (config & CPUCFG2_SCQ) {

		c->options |= LOONGARCH_CPU_SCQ;

		elf_hwcap |= HWCAP_LOONGARCH_SCQ;