Commit 1ddf1636 authored by Tariq Toukan's avatar Tariq Toukan Committed by Leon Romanovsky
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net/mlx5: Add IFC bit for TIR/SQ order capability 



Before this cap, firmware requested a certain creation order between TIR
objects and SQs of the same transport domain to properly support the
self loopback prevention feature. If order is not preserved, explicit
modify_tir operations are necessary after the opening of the SQs.

When set, this cap bit indicates that this firmware requirement /
limitation no longer holds.

Signed-off-by: default avatarTariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/1758521191-814350-2-git-send-email-tariqt@nvidia.com


Reviewed-by: default avatarCarolina Jubran <cjubran@nvidia.com>
Reviewed-by: default avatarDragos Tatulea <dtatulea@nvidia.com>
Signed-off-by: default avatarLeon Romanovsky <leon@kernel.org>
parent a3d076b0

include/linux/mlx5/mlx5_ifc.h

+2 −1
Original line number Diff line number Diff line
@@ -1895,7 +1895,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { 


	u8         reserved_at_2a0[0x7];

	u8         mkey_pcie_tph[0x1];

	u8         reserved_at_2a8[0x2];

	u8         reserved_at_2a8[0x1];

	u8         tis_tir_td_order[0x1];



	u8         psp[0x1];

	u8         shampo[0x1];