Commit 1df046ab authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 fixes from Catalin Marinas:

 - Cortex-A55 errata workaround (repeat TLBI)

 - AMPERE1 added to the Spectre-BHB affected list

 - MTE fix to avoid setting PG_mte_tagged if no tags have been touched
   on a page

 - Fixed typo in the SCTLR_EL1.SPINTMASK bit naming (the commit log has
   other typos)

 - perf: return value check in ali_drw_pmu_probe(),
   ALIBABA_UNCORE_DRW_PMU dependency on ACPI

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: Add AMPERE1 to the Spectre-BHB affected list
  arm64: mte: Avoid setting PG_mte_tagged if no tags cleared or restored
  MAINTAINERS: rectify file entry in ALIBABA PMU DRIVER
  drivers/perf: ALIBABA_UNCORE_DRW_PMU should depend on ACPI
  drivers/perf: fix return value check in ali_drw_pmu_probe()
  arm64: errata: Add Cortex-A55 to the repeat tlbi list
  arm64/sysreg: Fix typo in SCTR_EL1.SPINTMASK
parents 5e714bf1 0e5d5ae8

Documentation/arm64/silicon-errata.rst

+2 −0
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@@ -76,6 +76,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A55      | #1530923        | ARM64_ERRATUM_1530923       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A55      | #2441007        | ARM64_ERRATUM_2441007       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A57      | #832075         | ARM64_ERRATUM_832075        |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A57      | #852523         | N/A                         |

MAINTAINERS

+1 −1
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@@ -752,7 +752,7 @@ ALIBABA PMU DRIVER 
M:	Shuai Xue <xueshuai@linux.alibaba.com>

S:	Supported

F:	Documentation/admin-guide/perf/alibaba_pmu.rst

F:	drivers/perf/alibaba_uncore_dwr_pmu.c

F:	drivers/perf/alibaba_uncore_drw_pmu.c









ALIENWARE WMI DRIVER









L:	Dell.Client.Kernel@dell.com
































arch/arm64/Kconfig



+17
−0






























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@@ -632,6 +632,23 @@ config ARM64_ERRATUM_1530923







config ARM64_WORKAROUND_REPEAT_TLBI









	bool



















config ARM64_ERRATUM_2441007









	bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"









	default y









	select ARM64_WORKAROUND_REPEAT_TLBI









	help









	  This option adds a workaround for ARM Cortex-A55 erratum #2441007.



















	  Under very rare circumstances, affected Cortex-A55 CPUs









	  may not handle a race between a break-before-make sequence on one









	  CPU, and another CPU accessing the same page. This could allow a









	  store to a page that has been unmapped.



















	  Work around this by adding the affected CPUs to the list that needs









	  TLB sequences to be done twice.



















	  If unsure, say Y.



















config ARM64_ERRATUM_1286807









	bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"









	default y
































arch/arm64/include/asm/cputype.h



+4
−0






























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@@ -60,6 +60,7 @@







#define ARM_CPU_IMP_FUJITSU		0x46









#define ARM_CPU_IMP_HISI		0x48









#define ARM_CPU_IMP_APPLE		0x61









#define ARM_CPU_IMP_AMPERE		0xC0



















#define ARM_CPU_PART_AEM_V8		0xD0F









#define ARM_CPU_PART_FOUNDATION		0xD00








@@ -123,6 +124,8 @@







#define APPLE_CPU_PART_M1_ICESTORM_MAX	0x028









#define APPLE_CPU_PART_M1_FIRESTORM_MAX	0x029



















#define AMPERE_CPU_PART_AMPERE1		0xAC3



















#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)









#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)









#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)








@@ -172,6 +175,7 @@







#define MIDR_APPLE_M1_FIRESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO)









#define MIDR_APPLE_M1_ICESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_MAX)









#define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX)









#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)



















/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */









#define MIDR_FUJITSU_ERRATUM_010001		MIDR_FUJITSU_A64FX
































arch/arm64/kernel/cpu_errata.c



+5
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@@ -230,6 +230,11 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {







		ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe),









	},









#endif









#ifdef CONFIG_ARM64_ERRATUM_2441007









	{









		ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),









	},









#endif









#ifdef CONFIG_ARM64_ERRATUM_2441009









	{









		/* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */