Commit 1df3f01e authored by Marc Zyngier's avatar Marc Zyngier
Browse files

Merge branch kvm-arm64/resx into kvmarm-master/next 



* kvm-arm64/resx:
  : .
  : Add infrastructure to deal with the full gamut of RESx bits
  : for NV. As a result, it is now possible to have the expected
  : semantics for some bits such as SCTLR_EL2.SPAN.
  : .
  KVM: arm64: Add debugfs file dumping computed RESx values
  KVM: arm64: Add sanitisation to SCTLR_EL2
  KVM: arm64: Remove all traces of HCR_EL2.MIOCNCE
  KVM: arm64: Remove all traces of FEAT_TME
  KVM: arm64: Simplify handling of full register invalid constraint
  KVM: arm64: Get rid of FIXED_VALUE altogether
  KVM: arm64: Simplify handling of HCR_EL2.E2H RESx
  KVM: arm64: Move RESx into individual register descriptors
  KVM: arm64: Add RES1_WHEN_E2Hx constraints as configuration flags
  KVM: arm64: Add REQUIRES_E2H1 constraint as configuration flags
  KVM: arm64: Simplify FIXED_VALUE handling
  KVM: arm64: Convert HCR_EL2.RW to AS_RES1
  KVM: arm64: Correctly handle SCTLR_EL1 RES1 bits for unsupported features
  KVM: arm64: Allow RES1 bits to be inferred from configuration
  KVM: arm64: Inherit RESx bits from FGT register descriptors
  KVM: arm64: Extend unified RESx handling to runtime sanitisation
  KVM: arm64: Introduce data structure tracking both RES0 and RES1 bits
  KVM: arm64: Introduce standalone FGU computing primitive
  KVM: arm64: Remove duplicate configuration for SCTLR_EL1.{EE,E0E}
  arm64: Convert SCTLR_EL2 to sysreg infrastructure

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parents 3ef5ba66 edba4078

arch/arm64/include/asm/kvm_host.h

+32 −6
Original line number Diff line number Diff line
@@ -492,7 +492,6 @@ enum vcpu_sysreg { 
	DBGVCR32_EL2,	/* Debug Vector Catch Register */



	/* EL2 registers */

	SCTLR_EL2,	/* System Control Register (EL2) */

	ACTLR_EL2,	/* Auxiliary Control Register (EL2) */

	CPTR_EL2,	/* Architectural Feature Trap Register (EL2) */

	HACR_EL2,	/* Hypervisor Auxiliary Control Register */
@@ -523,6 +522,7 @@ enum vcpu_sysreg { 


	/* Anything from this can be RES0/RES1 sanitised */

	MARKER(__SANITISED_REG_START__),

	SCTLR_EL2,	/* System Control Register (EL2) */

	TCR2_EL2,	/* Extended Translation Control Register (EL2) */

	SCTLR2_EL2,	/* System Control Register 2 (EL2) */

	MDCR_EL2,	/* Monitor Debug Configuration Register (EL2) */
@@ -623,13 +623,39 @@ enum vcpu_sysreg { 
	NR_SYS_REGS	/* Nothing after this line! */

};



struct kvm_sysreg_masks {

	struct {

struct resx {

	u64	res0;

	u64	res1;

	} mask[NR_SYS_REGS - __SANITISED_REG_START__];

};



struct kvm_sysreg_masks {

	struct resx mask[NR_SYS_REGS - __SANITISED_REG_START__];

};



static inline struct resx __kvm_get_sysreg_resx(struct kvm_arch *arch,

						enum vcpu_sysreg sr)

{

	struct kvm_sysreg_masks *masks;



	masks = arch->sysreg_masks;

	if (likely(masks &&

		   sr >= __SANITISED_REG_START__ && sr < NR_SYS_REGS))

		return masks->mask[sr - __SANITISED_REG_START__];



	return (struct resx){};

}



#define kvm_get_sysreg_resx(k, sr) __kvm_get_sysreg_resx(&(k)->arch, (sr))



static inline void __kvm_set_sysreg_resx(struct kvm_arch *arch,

					 enum vcpu_sysreg sr, struct resx resx)

{

	arch->sysreg_masks->mask[sr - __SANITISED_REG_START__] = resx;

}



#define kvm_set_sysreg_resx(k, sr, resx)		\

	__kvm_set_sysreg_resx(&(k)->arch, (sr), (resx))



struct fgt_masks {

	const char	*str;

	u64		mask;
@@ -1604,7 +1630,7 @@ static inline bool kvm_arch_has_irq_bypass(void) 
}



void compute_fgu(struct kvm *kvm, enum fgt_group_id fgt);

void get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg, u64 *res0, u64 *res1);

struct resx get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg);

void check_feature_map(void);

void kvm_vcpu_load_fgt(struct kvm_vcpu *vcpu);

arch/arm64/include/asm/sysreg.h

+0 −7
Original line number Diff line number Diff line
@@ -504,7 +504,6 @@ 
#define SYS_VPIDR_EL2			sys_reg(3, 4, 0, 0, 0)

#define SYS_VMPIDR_EL2			sys_reg(3, 4, 0, 0, 5)



#define SYS_SCTLR_EL2			sys_reg(3, 4, 1, 0, 0)

#define SYS_ACTLR_EL2			sys_reg(3, 4, 1, 0, 1)

#define SYS_SCTLR2_EL2			sys_reg(3, 4, 1, 0, 3)

#define SYS_HCR_EL2			sys_reg(3, 4, 1, 1, 0)
@@ -836,12 +835,6 @@ 
#define SCTLR_ELx_A	 (BIT(1))

#define SCTLR_ELx_M	 (BIT(0))



/* SCTLR_EL2 specific flags. */

#define SCTLR_EL2_RES1	((BIT(4))  | (BIT(5))  | (BIT(11)) | (BIT(16)) | \

			 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \

			 (BIT(29)))



#define SCTLR_EL2_BT	(BIT(36))

#ifdef CONFIG_CPU_BIG_ENDIAN

#define ENDIAN_SET_EL2		SCTLR_ELx_EE

#else

arch/arm64/kvm/config.c

+233 −194

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arch/arm64/kvm/emulate-nested.c

+1 −9
Original line number Diff line number Diff line
@@ -2435,15 +2435,7 @@ static enum trap_behaviour compute_trap_behaviour(struct kvm_vcpu *vcpu, 


static u64 kvm_get_sysreg_res0(struct kvm *kvm, enum vcpu_sysreg sr)

{

	struct kvm_sysreg_masks *masks;



	/* Only handle the VNCR-backed regs for now */

	if (sr < __VNCR_START__)

		return 0;



	masks = kvm->arch.sysreg_masks;



	return masks->mask[sr - __SANITISED_REG_START__].res0;

	return kvm_get_sysreg_resx(kvm, sr).res0;

}



static bool check_fgt_bit(struct kvm_vcpu *vcpu, enum vcpu_sysreg sr,

arch/arm64/kvm/nested.c

+72 −79

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