Commit 1dfc7d1a authored by Alexey Charkov's avatar Alexey Charkov Committed by Ulf Hansson
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dt-bindings: mmc: vt8500-sdmmc: Convert to YAML 



Rewrite the textual description for the WonderMedia SDMMC controller
as YAML schema, and switch the filename to follow the compatible
string.

Signed-off-by: default avatarAlexey Charkov <alchark@gmail.com>
Reviewed-by: default avatarRob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250423-vt8500-sdmmc-binding-v2-1-ea4f17fd0638@gmail.com


Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent a0ba0461

Documentation/devicetree/bindings/mmc/vt8500-sdmmc.txt

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* Wondermedia WM8505/WM8650 SD/MMC Host Controller



This file documents differences between the core properties described

by mmc.txt and the properties used by the wmt-sdmmc driver.



Required properties:

- compatible: Should be "wm,wm8505-sdhc".

- interrupts: Two interrupts are required - regular irq and dma irq.



Optional properties:

- sdon-inverted: SD_ON bit is inverted on the controller



Examples:



sdhc@d800a000 {

	compatible = "wm,wm8505-sdhc";

	reg = <0xd800a000 0x1000>;

	interrupts = <20 21>;

	clocks = <&sdhc>;

	bus-width = <4>;

	sdon-inverted;

};

Documentation/devicetree/bindings/mmc/wm,wm8505-sdhc.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/mmc/wm,wm8505-sdhc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: WonderMedia SoC SDHCI Controller



maintainers:

  - Alexey Charkov <alchark@gmail.com>



allOf:

  - $ref: mmc-controller.yaml#



properties:

  compatible:

    oneOf:

      - const: wm,wm8505-sdhc

      - items:

          - const: wm,wm8650-sdhc

          - const: wm,wm8505-sdhc

      - items:

          - const: wm,wm8750-sdhc

          - const: wm,wm8505-sdhc

      - items:

          - const: wm,wm8850-sdhc

          - const: wm,wm8505-sdhc



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  interrupts:

    items:

      - description: SDMMC controller interrupt

      - description: SDMMC controller DMA interrupt



  sdon-inverted:

    type: boolean

    description: All chips before (not including) WM8505 rev. A2 treated their

      "clock stop" bit (register offset 0x08 a.k.a. SDMMC_BUSMODE, bit 0x10)

      as "set 1 to disable SD clock", while all the later versions treated it

      as "set 0 to disable SD clock". Set this property for later versions of

      wm,wm8505-sdhc. On wm,wm8650-sdhc and later this property is implied and

      does not need to be set explicitly



required:

  - compatible

  - reg

  - interrupts

  - clocks



unevaluatedProperties: false



examples:

  - |

    mmc@d800a000 {

        compatible = "wm,wm8505-sdhc";

        reg = <0xd800a000 0x1000>;

        interrupts = <20>, <21>;

        clocks = <&sdhc>;

        bus-width = <4>;

        sdon-inverted;

    };