Commit 1e05c5a0 authored by Karol Kolacinski's avatar Karol Kolacinski Committed by Tony Nguyen
Browse files

ice: remove SW side band access workaround for E825 



Due to the bug in FW/NVM autoload mechanism (wrong default
SB_REM_DEV_CTL register settings), the access to peer PHY and CGU
clients was disabled by default.

As the workaround solution, the register value was overwritten by the
driver at the probe or reset handling.
Remove workaround as it's not needed anymore. The fix in autoload
procedure has been provided with NVM 3.80 version.

NOTE: at the time the fix was provided in NVM, the E825C product was
not officially available on the market, so it's not expected this change
will cause regression when running with older driver/kernel versions.

Reviewed-by: default avatarMichal Swiatkowski <michal.swiatkowski@linux.intel.com>
Reviewed-by: default avatarPrzemek Kitszel <przemyslaw.kitszel@intel.com>
Signed-off-by: default avatarKarol Kolacinski <karol.kolacinski@intel.com>
Signed-off-by: default avatarGrzegorz Nitka <grzegorz.nitka@intel.com>
Reviewed-by: default avatarSimon Horman <horms@kernel.org>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
parent 517f7a08

drivers/net/ethernet/intel/ice/ice_ptp_hw.c

+0 −23
Original line number Diff line number Diff line
@@ -2630,25 +2630,6 @@ int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port) 
	return 0;

}



/**

 * ice_sb_access_ena_eth56g - Enable SB devices (PHY and others) access

 * @hw: pointer to HW struct

 * @enable: Enable or disable access

 *

 * Enable sideband devices (PHY and others) access.

 */

static void ice_sb_access_ena_eth56g(struct ice_hw *hw, bool enable)

{

	u32 val = rd32(hw, PF_SB_REM_DEV_CTL);



	if (enable)

		val |= BIT(eth56g_phy_0) | BIT(cgu) | BIT(eth56g_phy_1);

	else

		val &= ~(BIT(eth56g_phy_0) | BIT(cgu) | BIT(eth56g_phy_1));



	wr32(hw, PF_SB_REM_DEV_CTL, val);

}



/**

 * ice_ptp_init_phc_e825 - Perform E825 specific PHC initialization

 * @hw: pointer to HW struct
@@ -2659,8 +2640,6 @@ static void ice_sb_access_ena_eth56g(struct ice_hw *hw, bool enable) 
 */

static int ice_ptp_init_phc_e825(struct ice_hw *hw)

{

	ice_sb_access_ena_eth56g(hw, true);



	/* Initialize the Clock Generation Unit */

	return ice_init_cgu_e82x(hw);

}
@@ -2747,8 +2726,6 @@ static void ice_ptp_init_phy_e825(struct ice_hw *hw) 
	params->num_phys = 2;

	ptp->ports_per_phy = 4;

	ptp->num_lports = params->num_phys * ptp->ports_per_phy;



	ice_sb_access_ena_eth56g(hw, true);

}



/* E822 family functions