Commit 1e52db8a authored by Jouni Högander's avatar Jouni Högander
Browse files

drm/i915/psr: Rename has_psr2 as has_sel_update 



We are going to reuse has_psr2 for panel_replay as well. Rename it
as has_sel_update to avoid confusion.

v3: do not add has_psr check into psr2 case in intel_dp_compute_vsc_sdp
v2: Rebase

Signed-off-by: default avatarJouni Högander <jouni.hogander@intel.com>
Reviewed-by: default avatarAnimesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-2-jouni.hogander@intel.com
parent ce698dcf

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

+2 −2
Original line number Diff line number Diff line
@@ -251,9 +251,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, 
		drm_printf(&p, "sdp split: %s\n",

			   str_enabled_disabled(pipe_config->sdp_split_enable));



		drm_printf(&p, "psr: %s, psr2: %s, panel replay: %s, selective fetch: %s\n",

		drm_printf(&p, "psr: %s, selective update: %s, panel replay: %s, selective fetch: %s\n",

			   str_enabled_disabled(pipe_config->has_psr),

			   str_enabled_disabled(pipe_config->has_psr2),

			   str_enabled_disabled(pipe_config->has_sel_update),

			   str_enabled_disabled(pipe_config->has_panel_replay),

			   str_enabled_disabled(pipe_config->enable_psr2_sel_fetch));

	}

drivers/gpu/drm/i915/display/intel_display.c

+1 −1
Original line number Diff line number Diff line
@@ -5320,7 +5320,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, 
	 */

	if (current_config->has_panel_replay || pipe_config->has_panel_replay) {

		PIPE_CONF_CHECK_BOOL(has_psr);

		PIPE_CONF_CHECK_BOOL(has_psr2);

		PIPE_CONF_CHECK_BOOL(has_sel_update);

		PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);

		PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et);

		PIPE_CONF_CHECK_BOOL(has_panel_replay);

drivers/gpu/drm/i915/display/intel_display_types.h

+1 −1
Original line number Diff line number Diff line
@@ -1194,7 +1194,7 @@ struct intel_crtc_state { 


	/* PSR is supported but might not be enabled due the lack of enabled planes */

	bool has_psr;

	bool has_psr2;

	bool has_sel_update;

	bool enable_psr2_sel_fetch;

	bool enable_psr2_su_region_et;

	bool req_psr2_sdp_prior_scanline;

drivers/gpu/drm/i915/display/intel_dp.c

+1 −1
Original line number Diff line number Diff line
@@ -2663,7 +2663,7 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, 
	if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {

		intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,

						 vsc);

	} else if (crtc_state->has_psr2) {

	} else if (crtc_state->has_sel_update) {

		/*

		 * [PSR2 without colorimetry]

		 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11

drivers/gpu/drm/i915/display/intel_fbc.c

+1 −1
Original line number Diff line number Diff line
@@ -1251,7 +1251,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, 
	 * Recommendation is to keep this combination disabled

	 * Bspec: 50422 HSD: 14010260002

	 */

	if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_psr2) {

	if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update) {

		plane_state->no_fbc_reason = "PSR2 enabled";

		return 0;

	}