Commit 1e75d2e9 authored by John Madieu's avatar John Madieu Committed by Manivannan Sadhasivam
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PCI: rzg3s-host: Explicitly set class code for RZ/G3E compatibility 



Program the class code register explicitly during PCIe configuration
initialization. RZ/G3E requires this register to be set, while RZ/G3S
has these values as hardware defaults.

This configuration is harmless for RZ/G3S where these match the hardware
defaults, and necessary for RZ/G3E to properly identify the device as a
PCI bridge.

Signed-off-by: default avatarJohn Madieu <john.madieu.xa@bp.renesas.com>
Signed-off-by: default avatarManivannan Sadhasivam <mani@kernel.org>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> # RZ/V2N EVK
Tested-by: default avatarClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: default avatarClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://patch.msgid.link/20260306143423.19562-11-john.madieu.xa@bp.renesas.com
parent 5f2c4de7

drivers/pci/controller/pcie-rzg3s-host.c

+8 −0
Original line number Diff line number Diff line
@@ -1081,6 +1081,7 @@ static int rzg3s_pcie_set_max_link_speed(struct rzg3s_pcie_host *host) 
static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host)

{

	struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);

	u32 mask = GENMASK(31, 8);

	struct resource_entry *ft;

	struct resource *bus;

	u8 subordinate_bus;
@@ -1104,6 +1105,13 @@ static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host) 
	writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00L);

	writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00U);



	/*

	 * Explicitly program class code. RZ/G3E requires this configuration.

	 * Harmless for RZ/G3S where this matches the hardware default.

	 */

	rzg3s_pcie_update_bits(host->pcie, PCI_CLASS_REVISION, mask,

			       field_prep(mask, PCI_CLASS_BRIDGE_PCI_NORMAL));



	/* Disable access control to the CFGU */

	writel_relaxed(0, host->axi + RZG3S_PCI_PERM);