Commit 1ea07b5a authored by Max Merchel's avatar Max Merchel Committed by Frank Li
Browse files

ARM: dts: imx6qdl: add boot phase properties 



dtschema/schemas/bootph.yaml describe various node usage during
boot phases with DT.

All SoCs require buses (aips and spba), clock, iomuxc, ipu and
SOC access during boot process.

Signed-off-by: default avatarMax Merchel <Max.Merchel@ew.tq-group.com>
Signed-off-by: default avatarFrank Li <Frank.Li@nxp.com>
parent e65d9599

arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi

+6 −0
Original line number Diff line number Diff line
@@ -161,6 +161,7 @@ soc: soc { 
		compatible = "simple-bus";

		interrupt-parent = <&gpc>;

		ranges;

		bootph-all;



		dma_apbh: dma-controller@110000 {

			compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
@@ -309,6 +310,7 @@ aips1: bus@2000000 { /* AIPS1 */ 
			#size-cells = <1>;

			reg = <0x02000000 0x100000>;

			ranges;

			bootph-pre-ram;



			spba-bus@2000000 {

				compatible = "fsl,spba-bus", "simple-bus";
@@ -316,6 +318,7 @@ spba-bus@2000000 { 
				#size-cells = <1>;

				reg = <0x02000000 0x40000>;

				ranges;

				bootph-pre-ram;



				spdif: spdif@2004000 {

					compatible = "fsl,imx35-spdif";
@@ -932,6 +935,7 @@ mux: mux-controller { 
			iomuxc: pinctrl@20e0000 {

				compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";

				reg = <0x20e0000 0x4000>;

				bootph-pre-ram;

			};



			dcic1: dcic@20e4000 {
@@ -962,6 +966,7 @@ aips2: bus@2100000 { /* AIPS2 */ 
			#size-cells = <1>;

			reg = <0x02100000 0x100000>;

			ranges;

			bootph-pre-ram;



			crypto: crypto@2100000 {

				compatible = "fsl,sec-v4.0";
@@ -1332,6 +1337,7 @@ ipu1: ipu@2400000 { 
				 <&clks IMX6QDL_CLK_IPU1_DI1>;

			clock-names = "bus", "di0", "di1";

			resets = <&src 2>;

			bootph-all;



			ipu1_csi0: port@0 {

				reg = <0>;