Commit 1eccad35 authored by Fuad Tabba's avatar Fuad Tabba Committed by Marc Zyngier
Browse files

KVM: arm64: Fix the value of the CPTR_EL2 RES1 bitmask for nVHE 



Since the introduction of SME, bit 12 in CPTR_EL2 (nVHE) is TSM
for trapping SME, instead of RES1, as per ARM ARM DDI 0487K.a,
section D23.2.34.

Fix the value of CPTR_NVHE_EL2_RES1 to reflect that, and adjust
the code that relies on it accordingly.

Signed-off-by: default avatarFuad Tabba <tabba@google.com>
Link: https://lore.kernel.org/r/20241216105057.579031-15-tabba@google.com


Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent 8f7df795

arch/arm64/include/asm/kvm_arm.h

+1 −1
Original line number Diff line number Diff line
@@ -300,7 +300,7 @@ 
#define CPTR_EL2_TSM	(1 << 12)

#define CPTR_EL2_TFP	(1 << CPTR_EL2_TFP_SHIFT)

#define CPTR_EL2_TZ	(1 << 8)

#define CPTR_NVHE_EL2_RES1	0x000032ff /* known RES1 bits in CPTR_EL2 (nVHE) */

#define CPTR_NVHE_EL2_RES1	(BIT(13) | BIT(9) | GENMASK(7, 0))

#define CPTR_NVHE_EL2_RES0	(GENMASK(63, 32) |	\

				 GENMASK(29, 21) |	\

				 GENMASK(19, 14) |	\

arch/arm64/include/asm/kvm_emulate.h

+2 −2
Original line number Diff line number Diff line
@@ -640,8 +640,8 @@ static __always_inline void kvm_reset_cptr_el2(struct kvm_vcpu *vcpu) 


		if (vcpu_has_sve(vcpu) && guest_owns_fp_regs())

			val |= CPTR_EL2_TZ;

		if (cpus_have_final_cap(ARM64_SME))

			val &= ~CPTR_EL2_TSM;

		if (!cpus_have_final_cap(ARM64_SME))

			val |= CPTR_EL2_TSM;

	}



	kvm_write_cptr_el2(val);