Commit 1ed2d21d authored by Jason Gunthorpe's avatar Jason Gunthorpe Committed by Joerg Roedel
Browse files

iommu/amd: Remove the amd_iommu_domain_set_pt_root() and related 



Looks like many refactorings here have left this confused. There is only
one storage of the root/mode, it is in the iop struct.

increase_address_space() calls amd_iommu_domain_set_pgtable() with values
that it already stored in iop a few lines above.

amd_iommu_domain_clr_pt_root() is zero'ing memory we are about to free. It
used to protect against a double free of root, but that is gone now.

Remove amd_iommu_domain_set_pgtable(), amd_iommu_domain_set_pt_root(),
amd_iommu_domain_clr_pt_root() as they are all pointless.

Reviewed-by: default avatarVasant Hegde <vasant.hegde@amd.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/5-v2-831cdc4d00f3+1a315-amd_iopgtbl_jgg@nvidia.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent 322d889a

drivers/iommu/amd/amd_iommu.h

+0 −13
Original line number Diff line number Diff line
@@ -134,19 +134,6 @@ static inline void *iommu_phys_to_virt(unsigned long paddr) 
	return phys_to_virt(__sme_clr(paddr));

}



static inline

void amd_iommu_domain_set_pt_root(struct protection_domain *domain, u64 root)

{

	domain->iop.root = (u64 *)(root & PAGE_MASK);

	domain->iop.mode = root & 7; /* lowest 3 bits encode pgtable mode */

}



static inline

void amd_iommu_domain_clr_pt_root(struct protection_domain *domain)

{

	amd_iommu_domain_set_pt_root(domain, 0);

}



static inline int get_pci_sbdf_id(struct pci_dev *pdev)

{

	int seg = pci_domain_nr(pdev->bus);

drivers/iommu/amd/io_pgtable.c

+0 −24
Original line number Diff line number Diff line
@@ -132,18 +132,6 @@ static void free_sub_pt(u64 *root, int mode, struct list_head *freelist) 
	}

}



void amd_iommu_domain_set_pgtable(struct protection_domain *domain,

				  u64 *root, int mode)

{

	u64 pt_root;



	/* lowest 3 bits encode pgtable mode */

	pt_root = mode & 7;

	pt_root |= (u64)root;



	amd_iommu_domain_set_pt_root(domain, pt_root);

}



/*

 * This function is used to add another level to an IO page table. Adding

 * another level increases the size of the address space by 9 bits to a size up
@@ -176,12 +164,6 @@ static bool increase_address_space(struct protection_domain *domain, 
	domain->iop.mode += 1;

	amd_iommu_update_and_flush_device_table(domain);



	/*

	 * Device Table needs to be updated and flushed before the new root can

	 * be published.

	 */

	amd_iommu_domain_set_pgtable(domain, pte, domain->iop.mode);



	pte = NULL;

	ret = true;
@@ -560,23 +542,17 @@ static int iommu_v1_read_and_clear_dirty(struct io_pgtable_ops *ops, 
static void v1_free_pgtable(struct io_pgtable *iop)

{

	struct amd_io_pgtable *pgtable = container_of(iop, struct amd_io_pgtable, iop);

	struct protection_domain *dom;

	LIST_HEAD(freelist);



	if (pgtable->mode == PAGE_MODE_NONE)

		return;



	dom = container_of(pgtable, struct protection_domain, iop);



	/* Page-table is not visible to IOMMU anymore, so free it */

	BUG_ON(pgtable->mode < PAGE_MODE_NONE ||

	       pgtable->mode > PAGE_MODE_6_LEVEL);



	free_sub_pt(pgtable->root, pgtable->mode, &freelist);

	iommu_put_pages_list(&freelist);



	/* Update data structure */

	amd_iommu_domain_clr_pt_root(dom);

}



static struct io_pgtable *v1_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)