Commit 1ef05ef9 authored by Akhil P Oommen's avatar Akhil P Oommen Committed by Rob Clark
Browse files

drm/msm/a6xx: Sync latest register definitions 



Sync the latest register definitions from Mesa which includes the
updates for A8x family.

Co-developed-by: default avatarRob Clark <robin.clark@oss.qualcomm.com>
Signed-off-by: default avatarRob Clark <robin.clark@oss.qualcomm.com>
Signed-off-by: default avatarAkhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689009/
Message-ID: <20251118-kaana-gpu-support-v4-9-86eeb8e93fb6@oss.qualcomm.com>
parent 0d9f5ee4

drivers/gpu/drm/msm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -201,6 +201,7 @@ ADRENO_HEADERS = \ 
	generated/a6xx_perfcntrs.xml.h \

	generated/a7xx_enums.xml.h \

	generated/a7xx_perfcntrs.xml.h \

	generated/a8xx_enums.xml.h \

	generated/a6xx_gmu.xml.h \

	generated/adreno_common.xml.h \

	generated/adreno_pm4.xml.h \

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+8 −8
Original line number Diff line number Diff line
@@ -238,7 +238,7 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, 
		OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BOTH);



		OUT_PKT7(ring, CP_EVENT_WRITE, 1);

		OUT_RING(ring, LRZ_FLUSH);

		OUT_RING(ring, LRZ_FLUSH_INVALIDATE);



		OUT_PKT7(ring, CP_THREAD_CONTROL, 1);

		OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR);
@@ -381,7 +381,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 
		rbmemptr_stats(ring, index, alwayson_end));



	/* Write the fence to the scratch register */

	OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1);

	OUT_PKT4(ring, REG_A6XX_CP_SCRATCH(2), 1);

	OUT_RING(ring, submit->seqno);



	/*
@@ -522,7 +522,7 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 
		rbmemptr_stats(ring, index, alwayson_end));



	/* Write the fence to the scratch register */

	OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1);

	OUT_PKT4(ring, REG_A6XX_CP_SCRATCH(2), 1);

	OUT_RING(ring, submit->seqno);



	OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
@@ -1305,7 +1305,7 @@ static int hw_init(struct msm_gpu *gpu) 
	}



	if (adreno_is_a660_family(adreno_gpu))

		gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);

		gpu_write(gpu, REG_A7XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);



	/* Setting the mem pool size */

	if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu)) {
@@ -1754,10 +1754,10 @@ static int a6xx_fault_handler(void *arg, unsigned long iova, int flags, void *da 
	const char *block = "unknown";



	u32 scratch[] = {

			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),

			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),

			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),

			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)),

			gpu_read(gpu, REG_A6XX_CP_SCRATCH(4)),

			gpu_read(gpu, REG_A6XX_CP_SCRATCH(5)),

			gpu_read(gpu, REG_A6XX_CP_SCRATCH(6)),

			gpu_read(gpu, REG_A6XX_CP_SCRATCH(7)),

	};



	if (info)

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h

+4 −4
Original line number Diff line number Diff line
@@ -71,8 +71,8 @@ static const struct a6xx_cluster { 
	u32 sel_val;

} a6xx_clusters[] = {

	CLUSTER(CLUSTER_GRAS, a6xx_gras_cluster, 0, 0),

	CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rac, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0x0),

	CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rbp, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0x9),

	CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rac, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 0x0),

	CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rbp, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 0x9),

	CLUSTER(CLUSTER_PS, a6xx_ps_cluster, 0, 0),

	CLUSTER(CLUSTER_FE, a6xx_fe_cluster, 0, 0),

	CLUSTER(CLUSTER_PC_VS, a6xx_pc_vs_cluster, 0, 0),
@@ -303,8 +303,8 @@ static const u32 a660_registers[] = { 
static const struct a6xx_registers a6xx_reglist[] = {

	REGS(a6xx_registers, 0, 0),

	REGS(a660_registers, 0, 0),

	REGS(a6xx_rb_rac_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0),

	REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 9),

	REGS(a6xx_rb_rac_registers, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 0),

	REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 9),

};



static const u32 a6xx_ahb_registers[] = {

drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h

+4 −4
Original line number Diff line number Diff line
@@ -691,14 +691,14 @@ static const u32 gen7_0_0_tpl1_noncontext_pipe_lpac_registers[] = { 
static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_lpac_registers), 8));



static const struct gen7_sel_reg  gen7_0_0_rb_rac_sel = {

	.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,

	.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,

	.host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST,

	.cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD,

	.val = 0x0,

};



static const struct gen7_sel_reg gen7_0_0_rb_rbp_sel = {

	.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,

	.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,

	.host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST,

	.cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD,

	.val = 0x9,

};

drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h

+4 −4
Original line number Diff line number Diff line
@@ -478,14 +478,14 @@ static const u32 gen7_2_0_sp_noncontext_pipe_lpac_hlsq_state_registers[] = { 
static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_noncontext_pipe_lpac_hlsq_state_registers), 8));



static const struct gen7_sel_reg  gen7_2_0_rb_rac_sel = {

	.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,

	.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,

	.host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST,

	.cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD,

	.val = 0x0,

};



static const struct gen7_sel_reg gen7_2_0_rb_rbp_sel = {

	.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,

	.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,

	.host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST,

	.cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD,

	.val = 0x9,

};