dt-bindings: mtd: cadence: convert cadence-nand-controller.txt to yaml

* Cadence NAND controller

Required properties:

  - compatible : "cdns,hp-nfc"

  - reg : Contains two entries, each of which is a tuple consisting of a

	  physical address and length. The first entry is the address and

	  length of the controller register set. The second entry is the

	  address and length of the Slave DMA data port.

  - reg-names: should contain "reg" and "sdma"

  - #address-cells: should be 1. The cell encodes the chip select connection.

  - #size-cells : should be 0.

  - interrupts : The interrupt number.

  - clocks: phandle of the controller core clock (nf_clk).

Optional properties:

  - dmas: shall reference DMA channel associated to the NAND controller

  - cdns,board-delay-ps : Estimated Board delay. The value includes the total

    round trip delay for the signals and is used for deciding on values

    associated with data read capture. The example formula for SDR mode is

    the following:

    board delay = RE#PAD delay + PCB trace to device + PCB trace from device

    + DQ PAD delay

Child nodes represent the available NAND chips.

Required properties of NAND chips:

  - reg: shall contain the native Chip Select ids from 0 to max supported by

    the cadence nand flash controller

See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on

generic bindings.

Example:

nand_controller: nand-controller@60000000 {

	  compatible = "cdns,hp-nfc";

	  #address-cells = <1>;

	  #size-cells = <0>;

	  reg = <0x60000000 0x10000>, <0x80000000 0x10000>;

	  reg-names = "reg", "sdma";

	  clocks = <&nf_clk>;

	  cdns,board-delay-ps = <4830>;

	  interrupts = <2 0>;

	  nand@0 {

	      reg = <0>;

	      label = "nand-1";

	  };

	  nand@1 {

	      reg = <1>;

	      label = "nand-2";

	  };

};

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/mtd/cdns,hp-nfc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cadence NAND controller

maintainers:

  - Niravkumar L Rabara <niravkumar.l.rabara@intel.com>

allOf:

  - $ref: nand-controller.yaml

properties:

  compatible:

    items:

      - const: cdns,hp-nfc

  reg:

    items:

      - description: Controller register set

      - description: Slave DMA data port register set

  reg-names:

    items:

      - const: reg

      - const: sdma

  interrupts:

    maxItems: 1

  clocks:

    maxItems: 1

  dmas:

    maxItems: 1

  cdns,board-delay-ps:

    description: |

      Estimated Board delay. The value includes the total round trip

      delay for the signals and is used for deciding on values associated

      with data read capture. The example formula for SDR mode is the

      following.

      board delay = RE#PAD delay + PCB trace to device + PCB trace from device

      + DQ PAD delay

required:

  - compatible

  - reg

  - reg-names

  - interrupts

  - clocks

unevaluatedProperties: false

examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    nand-controller@10b80000 {

        compatible = "cdns,hp-nfc";

        reg = <0x10b80000 0x10000>,

              <0x10840000 0x10000>;

        reg-names = "reg", "sdma";

        #address-cells = <1>;

        #size-cells = <0>;

        interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&nf_clk>;

        cdns,board-delay-ps = <4830>;

        nand@0 {

            reg = <0>;

        };

    };

CADENCE NAND DRIVER

L:	linux-mtd@lists.infradead.org

S:	Orphan

F:	Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt

F:	Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml

F:	drivers/mtd/nand/raw/cadence-nand-controller.c

CADENCE USB3 DRD IP DRIVER