Unverified Commit 1f2d68c3 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v6.19-tag1' of... 

Merge tag 'renesas-clk-for-v6.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Various fixes for the module reset procedure on R-Car Gen4 SoCs
 - Add ADC and thermal (TSU) clocks on RZ/T2H and RZ/N2H
 - Add USB clocks and resets on RZ/G3E
 - Add ISP and display (DSI, LCDC) clocks and resets on RZ/V2H and RZ/V2N
 - Add thermal (TSU) and RTC clocks and resets on RZ/V2H
 - Add reset support on RZ/T2H and RZ/N2H
 - Fix the module stop disable procedure on RZ/T2H and RZ/N2H
 - Add camera (CRU) clocks and resets on RZ/V2N

* tag 'renesas-clk-for-v6.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (21 commits)
  clk: renesas: r9a09g056: Add clock and reset entries for ISP
  clk: renesas: r9a09g056: Add support for PLLVDO, CRU clocks, and resets
  clk: renesas: r9a09g056: Add clocks and resets for DSI and LCDC modules
  clk: renesas: r9a09g077: Add TSU module clock
  clk: renesas: r9a09g057: Add clock and reset entries for DSI and LCDC
  clk: renesas: rzv2h: Add support for DSI clocks
  clk: renesas: rzv2h: Use GENMASK for PLL fields
  clk: renesas: rzv2h: Add instance field to struct pll
  clk: renesas: r9a09g057: Add clock and reset entries for RTC
  clk: renesas: cpg-mssr: Spelling s/offets/offsets/
  clk: renesas: r9a09g057: Add clock and reset entries for TSU
  clk: renesas: cpg-mssr: Add read-back and delay handling for RZ/T2H MSTP
  clk: renesas: cpg-mssr: Add module reset support for RZ/T2H
  clk: renesas: r9a09g057: Add clock and reset entries for ISP
  clk: renesas: r9a09g047: Add clock and reset entries for USB2
  clk: renesas: Use IS_ERR() for pointers that cannot be NULL
  dt-bindings: clock: renesas,r9a09g047-cpg: Add USB2 PHY core clocks
  clk: renesas: cpg-lib: Remove unneeded semicolon
  clk: renesas: r9a09g077: Add ADC module clocks
  clk: renesas: cpg-mssr: Read back reset registers to assure values latched
  ...
parents 3a866087 07525a69

drivers/clk/renesas/r9a09g047-cpg.c

+17 −1
Original line number Diff line number Diff line
@@ -16,7 +16,7 @@ 


enum clk_ids {

	/* Core Clock Outputs exported to DT */

	LAST_DT_CORE_CLK = R9A09G047_USB3_0_CLKCORE,

	LAST_DT_CORE_CLK = R9A09G047_USB2_0_CLK_CORE1,



	/* External Input Clocks */

	CLK_AUDIO_EXTAL,
@@ -177,6 +177,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { 
		 CDDIV1_DIVCTL3, dtable_1_8),

	DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),

	DEF_FIXED("spi_clk_spi", R9A09G047_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2),

	DEF_FIXED("usb2_0_clk_core0", R9A09G047_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1),

	DEF_FIXED("usb2_0_clk_core1", R9A09G047_USB2_0_CLK_CORE1, CLK_QEXTAL, 1, 1),

	DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G047_GBETH_0_CLK_PTP_REF_I,

		  CLK_PLLETH_DIV_125_FIX, 1, 1),

	DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G047_GBETH_1_CLK_PTP_REF_I,
@@ -282,6 +284,16 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { 
						BUS_MSTOP(7, BIT(12))),

	DEF_MOD("usb3_0_pclk_usbtst",		CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,

						BUS_MSTOP(7, BIT(14))),

	DEF_MOD("usb2_0_u2h0_hclk",		CLK_PLLDTY_DIV8, 11, 3, 5, 19,

						BUS_MSTOP(7, BIT(7))),

	DEF_MOD("usb2_0_u2h1_hclk",		CLK_PLLDTY_DIV8, 11, 4, 5, 20,

						BUS_MSTOP(7, BIT(8))),

	DEF_MOD("usb2_0_u2p_exr_cpuclk",	CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,

						BUS_MSTOP(7, BIT(9))),

	DEF_MOD("usb2_0_pclk_usbtst0",		CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22,

						BUS_MSTOP(7, BIT(10))),

	DEF_MOD("usb2_0_pclk_usbtst1",		CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,

						BUS_MSTOP(7, BIT(11))),

	DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,

						BUS_MSTOP(8, BIT(5)), 1),

	DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
@@ -359,6 +371,10 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = { 
	DEF_RST(10, 8, 4, 25),		/* SDHI_1_IXRST */

	DEF_RST(10, 9, 4, 26),		/* SDHI_2_IXRST */

	DEF_RST(10, 10, 4, 27),		/* USB3_0_ARESETN */

	DEF_RST(10, 12, 4, 29),		/* USB2_0_U2H0_HRESETN */

	DEF_RST(10, 13, 4, 30),		/* USB2_0_U2H1_HRESETN */

	DEF_RST(10, 14, 4, 31),		/* USB2_0_U2P_EXL_SYSRST */

	DEF_RST(10, 15, 5, 0),		/* USB2_0_PRESETN */

	DEF_RST(11, 0, 5, 1),		/* GBETH_0_ARESETN_I */

	DEF_RST(11, 1, 5, 2),		/* GBETH_1_ARESETN_I */

	DEF_RST(12, 5, 5, 22),		/* CRU_0_PRESETN */

drivers/clk/renesas/r9a09g056-cpg.c

+109 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
 */



#include <linux/clk-provider.h>

#include <linux/clk/renesas.h>

#include <linux/device.h>

#include <linux/init.h>

#include <linux/kernel.h>
@@ -28,7 +29,9 @@ enum clk_ids { 
	CLK_PLLCLN,

	CLK_PLLDTY,

	CLK_PLLCA55,

	CLK_PLLVDO,

	CLK_PLLETH,

	CLK_PLLDSI,

	CLK_PLLGPU,



	/* Internal Core Clocks */
@@ -47,6 +50,10 @@ enum clk_ids { 
	CLK_PLLDTY_ACPU_DIV2,

	CLK_PLLDTY_ACPU_DIV4,

	CLK_PLLDTY_DIV8,

	CLK_PLLDTY_DIV16,

	CLK_PLLVDO_CRU0,

	CLK_PLLVDO_CRU1,

	CLK_PLLVDO_ISP,

	CLK_PLLETH_DIV_250_FIX,

	CLK_PLLETH_DIV_125_FIX,

	CLK_CSDIV_PLLETH_GBE0,
@@ -55,6 +62,9 @@ enum clk_ids { 
	CLK_SMUX2_GBE0_RXCLK,

	CLK_SMUX2_GBE1_TXCLK,

	CLK_SMUX2_GBE1_RXCLK,

	CLK_CDIV4_PLLETH_LPCLK,

	CLK_PLLETH_LPCLK_GEAR,

	CLK_PLLDSI_GEAR,

	CLK_PLLGPU_GEAR,



	/* Module Clocks */
@@ -69,6 +79,12 @@ static const struct clk_div_table dtable_1_8[] = { 
	{0, 0},

};



static const struct clk_div_table dtable_2_4[] = {

	{0, 2},

	{1, 4},

	{0, 0},

};



static const struct clk_div_table dtable_2_16[] = {

	{0, 2},

	{1, 4},
@@ -77,6 +93,26 @@ static const struct clk_div_table dtable_2_16[] = { 
	{0, 0},

};



static const struct clk_div_table dtable_2_32[] = {

	{0, 2},

	{1, 4},

	{2, 6},

	{3, 8},

	{4, 10},

	{5, 12},

	{6, 14},

	{7, 16},

	{8, 18},

	{9, 20},

	{10, 22},

	{11, 24},

	{12, 26},

	{13, 28},

	{14, 30},

	{15, 32},

	{0, 0},

};



static const struct clk_div_table dtable_2_64[] = {

	{0, 2},

	{1, 4},
@@ -93,6 +129,17 @@ static const struct clk_div_table dtable_2_100[] = { 
	{0, 0},

};



static const struct clk_div_table dtable_16_128[] = {

	{0, 16},

	{1, 32},

	{2, 64},

	{3, 128},

	{0, 0},

};



RZV2H_CPG_PLL_DSI_LIMITS(rzv2n_cpg_pll_dsi_limits);

#define PLLDSI		PLL_PACK_LIMITS(0xc0, 1, 0, &rzv2n_cpg_pll_dsi_limits)



/* Mux clock tables */

static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };

static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
@@ -112,7 +159,9 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = { 
	DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),

	DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),

	DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),

	DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),

	DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),

	DEF_PLLDSI(".plldsi", CLK_PLLDSI, CLK_QEXTAL, PLLDSI),

	DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU),



	/* Internal Core Clocks */
@@ -134,6 +183,11 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = { 
	DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),

	DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),

	DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),

	DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),



	DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),

	DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4),

	DEF_DDIV(".pllvdo_isp",  CLK_PLLVDO_ISP,  CLK_PLLVDO, CDDIV2_DIVCTL3, dtable_2_64),



	DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),

	DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
@@ -145,6 +199,12 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = { 
	DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),

	DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),

	DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),

	DEF_FIXED(".cdiv4_plleth_lpclk", CLK_CDIV4_PLLETH_LPCLK, CLK_PLLETH, 1, 4),

	DEF_CSDIV(".plleth_lpclk_gear", CLK_PLLETH_LPCLK_GEAR, CLK_CDIV4_PLLETH_LPCLK,

		  CSDIV0_DIVCTL2, dtable_16_128),



	DEF_PLLDSI_DIV(".plldsi_gear", CLK_PLLDSI_GEAR, CLK_PLLDSI,

		       CSDIV1_DIVCTL2, dtable_2_32),



	DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
@@ -289,6 +349,42 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = { 
						BUS_MSTOP(8, BIT(6))),

	DEF_MOD("gbeth_1_aclk_i",		CLK_PLLDTY_DIV8, 12, 3, 6, 3,

						BUS_MSTOP(8, BIT(6))),

	DEF_MOD("cru_0_aclk",			CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,

						BUS_MSTOP(9, BIT(4))),

	DEF_MOD_NO_PM("cru_0_vclk",		CLK_PLLVDO_CRU0, 13, 3, 6, 19,

						BUS_MSTOP(9, BIT(4))),

	DEF_MOD("cru_0_pclk",			CLK_PLLDTY_DIV16, 13, 4, 6, 20,

						BUS_MSTOP(9, BIT(4))),

	DEF_MOD("cru_1_aclk",			CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21,

						BUS_MSTOP(9, BIT(5))),

	DEF_MOD_NO_PM("cru_1_vclk",		CLK_PLLVDO_CRU1, 13, 6, 6, 22,

						BUS_MSTOP(9, BIT(5))),

	DEF_MOD("cru_1_pclk",			CLK_PLLDTY_DIV16, 13, 7, 6, 23,

						BUS_MSTOP(9, BIT(5))),

	DEF_MOD("isp_0_reg_aclk",		CLK_PLLDTY_ACPU_DIV2, 14, 2, 7, 2,

						BUS_MSTOP(9, BIT(8))),

	DEF_MOD("isp_0_pclk",			CLK_PLLDTY_DIV16, 14, 3, 7, 3,

						BUS_MSTOP(9, BIT(8))),

	DEF_MOD("isp_0_vin_aclk",		CLK_PLLDTY_ACPU_DIV2, 14, 4, 7, 4,

						BUS_MSTOP(9, BIT(9))),

	DEF_MOD("isp_0_isp_sclk",		CLK_PLLVDO_ISP, 14, 5, 7, 5,

						BUS_MSTOP(9, BIT(9))),

	DEF_MOD("dsi_0_pclk",			CLK_PLLDTY_DIV16, 14, 8, 7, 8,

						BUS_MSTOP(9, BIT(14) | BIT(15))),

	DEF_MOD("dsi_0_aclk",			CLK_PLLDTY_ACPU_DIV2, 14, 9, 7, 9,

						BUS_MSTOP(9, BIT(14) | BIT(15))),

	DEF_MOD("dsi_0_vclk1",			CLK_PLLDSI_GEAR, 14, 10, 7, 10,

						BUS_MSTOP(9, BIT(14) | BIT(15))),

	DEF_MOD("dsi_0_lpclk",			CLK_PLLETH_LPCLK_GEAR, 14, 11, 7, 11,

						BUS_MSTOP(9, BIT(14) | BIT(15))),

	DEF_MOD("dsi_0_pllref_clk",		CLK_QEXTAL, 14, 12, 7, 12,

						BUS_MSTOP(9, BIT(14) | BIT(15))),

	DEF_MOD("lcdc_0_clk_a",			CLK_PLLDTY_ACPU_DIV2, 14, 13, 7, 13,

						BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),

	DEF_MOD("lcdc_0_clk_p",			CLK_PLLDTY_DIV16, 14, 14, 7, 14,

						BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),

	DEF_MOD("lcdc_0_clk_d",			CLK_PLLDSI_GEAR, 14, 15, 7, 15,

						BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),

	DEF_MOD("gpu_0_clk",			CLK_PLLGPU_GEAR, 15, 0, 7, 16,

						BUS_MSTOP(3, BIT(4))),

	DEF_MOD("gpu_0_axi_clk",		CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
@@ -335,6 +431,19 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = { 
	DEF_RST(10, 15, 5, 0),		/* USB2_0_PRESETN */

	DEF_RST(11, 0, 5, 1),		/* GBETH_0_ARESETN_I */

	DEF_RST(11, 1, 5, 2),		/* GBETH_1_ARESETN_I */

	DEF_RST(12, 5, 5, 22),		/* CRU_0_PRESETN */

	DEF_RST(12, 6, 5, 23),		/* CRU_0_ARESETN */

	DEF_RST(12, 7, 5, 24),		/* CRU_0_S_RESETN */

	DEF_RST(12, 8, 5, 25),		/* CRU_1_PRESETN */

	DEF_RST(12, 9, 5, 26),		/* CRU_1_ARESETN */

	DEF_RST(12, 10, 5, 27),		/* CRU_1_S_RESETN */

	DEF_RST(13, 1, 6, 2),		/* ISP_0_VIN_ARESETN */

	DEF_RST(13, 2, 6, 3),		/* ISP_0_REG_ARESETN */

	DEF_RST(13, 3, 6, 4),		/* ISP_0_ISP_SRESETN */

	DEF_RST(13, 4, 6, 5),		/* ISP_0_PRESETN */

	DEF_RST(13, 7, 6, 8),		/* DSI_0_PRESETN */

	DEF_RST(13, 8, 6, 9),		/* DSI_0_ARESETN */

	DEF_RST(13, 12, 6, 13),		/* LCDC_0_RESET_N */

	DEF_RST(13, 13, 6, 14),		/* GPU_0_RESETN */

	DEF_RST(13, 14, 6, 15),		/* GPU_0_AXI_RESETN */

	DEF_RST(13, 15, 6, 16),		/* GPU_0_ACE_RESETN */

drivers/clk/renesas/r9a09g057-cpg.c

+86 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
 */



#include <linux/clk-provider.h>

#include <linux/clk/renesas.h>

#include <linux/device.h>

#include <linux/init.h>

#include <linux/kernel.h>
@@ -30,6 +31,7 @@ enum clk_ids { 
	CLK_PLLCA55,

	CLK_PLLVDO,

	CLK_PLLETH,

	CLK_PLLDSI,

	CLK_PLLGPU,



	/* Internal Core Clocks */
@@ -55,6 +57,7 @@ enum clk_ids { 
	CLK_PLLVDO_CRU1,

	CLK_PLLVDO_CRU2,

	CLK_PLLVDO_CRU3,

	CLK_PLLVDO_ISP,

	CLK_PLLETH_DIV_250_FIX,

	CLK_PLLETH_DIV_125_FIX,

	CLK_CSDIV_PLLETH_GBE0,
@@ -63,6 +66,9 @@ enum clk_ids { 
	CLK_SMUX2_GBE0_RXCLK,

	CLK_SMUX2_GBE1_TXCLK,

	CLK_SMUX2_GBE1_RXCLK,

	CLK_CDIV4_PLLETH_LPCLK,

	CLK_PLLETH_LPCLK_GEAR,

	CLK_PLLDSI_GEAR,

	CLK_PLLGPU_GEAR,



	/* Module Clocks */
@@ -91,6 +97,26 @@ static const struct clk_div_table dtable_2_16[] = { 
	{0, 0},

};



static const struct clk_div_table dtable_2_32[] = {

	{0, 2},

	{1, 4},

	{2, 6},

	{3, 8},

	{4, 10},

	{5, 12},

	{6, 14},

	{7, 16},

	{8, 18},

	{9, 20},

	{10, 22},

	{11, 24},

	{12, 26},

	{13, 28},

	{14, 30},

	{15, 32},

	{0, 0},

};



static const struct clk_div_table dtable_2_64[] = {

	{0, 2},

	{1, 4},
@@ -107,6 +133,17 @@ static const struct clk_div_table dtable_2_100[] = { 
	{0, 0},

};



static const struct clk_div_table dtable_16_128[] = {

	{0, 16},

	{1, 32},

	{2, 64},

	{3, 128},

	{0, 0},

};



RZV2H_CPG_PLL_DSI_LIMITS(rzv2h_cpg_pll_dsi_limits);

#define PLLDSI		PLL_PACK_LIMITS(0xc0, 1, 0, &rzv2h_cpg_pll_dsi_limits)



/* Mux clock tables */

static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };

static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
@@ -128,6 +165,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { 
	DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),

	DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),

	DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),

	DEF_PLLDSI(".plldsi", CLK_PLLDSI, CLK_QEXTAL, PLLDSI),

	DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU),



	/* Internal Core Clocks */
@@ -157,6 +195,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { 
	DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4),

	DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4),

	DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4),

	DEF_DDIV(".pllvdo_isp",  CLK_PLLVDO_ISP,  CLK_PLLVDO, CDDIV2_DIVCTL3, dtable_2_64),



	DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),

	DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
@@ -168,6 +207,12 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { 
	DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),

	DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),

	DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),

	DEF_FIXED(".cdiv4_plleth_lpclk", CLK_CDIV4_PLLETH_LPCLK, CLK_PLLETH, 1, 4),

	DEF_CSDIV(".plleth_lpclk_gear", CLK_PLLETH_LPCLK_GEAR, CLK_CDIV4_PLLETH_LPCLK,

		  CSDIV0_DIVCTL2, dtable_16_128),



	DEF_PLLDSI_DIV(".plldsi_gear", CLK_PLLDSI_GEAR, CLK_PLLDSI,

		       CSDIV1_DIVCTL2, dtable_2_32),



	DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
@@ -239,6 +284,8 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { 
						BUS_MSTOP(5, BIT(13))),

	DEF_MOD("wdt_3_clk_loco",		CLK_QEXTAL, 5, 2, 2, 18,

						BUS_MSTOP(5, BIT(13))),

	DEF_MOD("rtc_0_clk_rtc",		CLK_PLLCM33_DIV16, 5, 3, 2, 19,

						BUS_MSTOP(3, BIT(11) | BIT(12))),

	DEF_MOD("rspi_0_pclk",			CLK_PLLCLN_DIV8, 5, 4, 2, 20,

						BUS_MSTOP(11, BIT(0))),

	DEF_MOD("rspi_0_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 5, 2, 21,
@@ -371,12 +418,40 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { 
						BUS_MSTOP(9, BIT(7))),

	DEF_MOD("cru_3_pclk",			CLK_PLLDTY_DIV16, 13, 13, 6, 29,

						BUS_MSTOP(9, BIT(7))),

	DEF_MOD("isp_0_reg_aclk",		CLK_PLLDTY_ACPU_DIV2, 14, 2, 7, 2,

						BUS_MSTOP(9, BIT(8))),

	DEF_MOD("isp_0_pclk",			CLK_PLLDTY_DIV16, 14, 3, 7, 3,

						BUS_MSTOP(9, BIT(8))),

	DEF_MOD("isp_0_vin_aclk",		CLK_PLLDTY_ACPU_DIV2, 14, 4, 7, 4,

						BUS_MSTOP(9, BIT(9))),

	DEF_MOD("isp_0_isp_sclk",		CLK_PLLVDO_ISP, 14, 5, 7, 5,

						BUS_MSTOP(9, BIT(9))),

	DEF_MOD("dsi_0_pclk",			CLK_PLLDTY_DIV16, 14, 8, 7, 8,

						BUS_MSTOP(9, BIT(14) | BIT(15))),

	DEF_MOD("dsi_0_aclk",			CLK_PLLDTY_ACPU_DIV2, 14, 9, 7, 9,

						BUS_MSTOP(9, BIT(14) | BIT(15))),

	DEF_MOD("dsi_0_vclk1",			CLK_PLLDSI_GEAR, 14, 10, 7, 10,

						BUS_MSTOP(9, BIT(14) | BIT(15))),

	DEF_MOD("dsi_0_lpclk",			CLK_PLLETH_LPCLK_GEAR, 14, 11, 7, 11,

						BUS_MSTOP(9, BIT(14) | BIT(15))),

	DEF_MOD("dsi_0_pllref_clk",		CLK_QEXTAL, 14, 12, 7, 12,

						BUS_MSTOP(9, BIT(14) | BIT(15))),

	DEF_MOD("lcdc_0_clk_a",			CLK_PLLDTY_ACPU_DIV2, 14, 13, 7, 13,

						BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),

	DEF_MOD("lcdc_0_clk_p",			CLK_PLLDTY_DIV16, 14, 14, 7, 14,

						BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),

	DEF_MOD("lcdc_0_clk_d",			CLK_PLLDSI_GEAR, 14, 15, 7, 15,

						BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),

	DEF_MOD("gpu_0_clk",			CLK_PLLGPU_GEAR, 15, 0, 7, 16,

						BUS_MSTOP(3, BIT(4))),

	DEF_MOD("gpu_0_axi_clk",		CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,

						BUS_MSTOP(3, BIT(4))),

	DEF_MOD("gpu_0_ace_clk",		CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,

						BUS_MSTOP(3, BIT(4))),

	DEF_MOD("tsu_0_pclk",			CLK_QEXTAL, 16, 9, 8, 9,

						BUS_MSTOP(5, BIT(2))),

	DEF_MOD("tsu_1_pclk",			CLK_QEXTAL, 16, 10, 8, 10,

						BUS_MSTOP(2, BIT(15))),

};



static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
@@ -401,6 +476,8 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = { 
	DEF_RST(7, 6, 3, 7),		/* WDT_1_RESET */

	DEF_RST(7, 7, 3, 8),		/* WDT_2_RESET */

	DEF_RST(7, 8, 3, 9),		/* WDT_3_RESET */

	DEF_RST(7, 9, 3, 10),		/* RTC_0_RST_RTC */

	DEF_RST(7, 10, 3, 11),		/* RTC_0_RST_RTC_V */

	DEF_RST(7, 11, 3, 12),		/* RSPI_0_PRESETN */

	DEF_RST(7, 12, 3, 13),		/* RSPI_0_TRESETN */

	DEF_RST(7, 13, 3, 14),		/* RSPI_1_PRESETN */
@@ -442,9 +519,18 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = { 
	DEF_RST(12, 14, 5, 31),		/* CRU_3_PRESETN */

	DEF_RST(12, 15, 6, 0),		/* CRU_3_ARESETN */

	DEF_RST(13, 0, 6, 1),		/* CRU_3_S_RESETN */

	DEF_RST(13, 1, 6, 2),		/* ISP_0_VIN_ARESETN */

	DEF_RST(13, 2, 6, 3),		/* ISP_0_REG_ARESETN */

	DEF_RST(13, 3, 6, 4),		/* ISP_0_ISP_SRESETN */

	DEF_RST(13, 4, 6, 5),		/* ISP_0_PRESETN */

	DEF_RST(13, 7, 6, 8),		/* DSI_0_PRESETN */

	DEF_RST(13, 8, 6, 9),		/* DSI_0_ARESETN */

	DEF_RST(13, 12, 6, 13),		/* LCDC_0_RESET_N */

	DEF_RST(13, 13, 6, 14),		/* GPU_0_RESETN */

	DEF_RST(13, 14, 6, 15),		/* GPU_0_AXI_RESETN */

	DEF_RST(13, 15, 6, 16),		/* GPU_0_ACE_RESETN */

	DEF_RST(15, 7, 7, 8),		/* TSU_0_PRESETN */

	DEF_RST(15, 8, 7, 9),		/* TSU_1_PRESETN */

};



const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = {

drivers/clk/renesas/r9a09g077-cpg.c

+4 −0
Original line number Diff line number Diff line
@@ -188,6 +188,10 @@ static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = { 
	DEF_MOD("sci4fck", 12, CLK_SCI4ASYNC),

	DEF_MOD("iic0", 100, R9A09G077_CLK_PCLKL),

	DEF_MOD("iic1", 101, R9A09G077_CLK_PCLKL),

	DEF_MOD("adc0", 206, R9A09G077_CLK_PCLKH),

	DEF_MOD("adc1", 207, R9A09G077_CLK_PCLKH),

	DEF_MOD("adc2", 225, R9A09G077_CLK_PCLKM),

	DEF_MOD("tsu", 307, R9A09G077_CLK_PCLKL),

	DEF_MOD("gmac0", 400, R9A09G077_CLK_PCLKM),

	DEF_MOD("ethsw", 401, R9A09G077_CLK_PCLKM),

	DEF_MOD("ethss", 403, R9A09G077_CLK_PCLKM),

drivers/clk/renesas/rcar-cpg-lib.c

+1 −1
Original line number Diff line number Diff line
@@ -35,7 +35,7 @@ void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set) 
	val |= set;

	writel(val, reg);

	spin_unlock_irqrestore(&cpg_lock, flags);

};

}



static int cpg_simple_notifier_call(struct notifier_block *nb,

				    unsigned long action, void *data)