Commit 1f4449e1 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
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arm64: dts: renesas: r8a779a0: Add SYS-DMAC nodes 



Add device nodes for the Direct Memory Access Controller for System
(SYS-DMAC) instances on the Renesas R-Car V3U (r8a779a0) SoC.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20210107182045.1948037-1-geert+renesas@glider.be
parent dfacaef9

arch/arm64/boot/dts/renesas/r8a779a0.dtsi

+58 −0
Original line number Diff line number Diff line
@@ -264,6 +264,64 @@ scif0: serial@e6e60000 { 
			status = "disabled";

		};



		dmac1: dma-controller@e7350000 {

			compatible = "renesas,dmac-r8a779a0";

			reg = <0 0xe7350000 0 0x1000>,

			      <0 0xe7300000 0 0x10000>;

			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "error",

					  "ch0", "ch1", "ch2", "ch3", "ch4",

					  "ch5", "ch6", "ch7", "ch8", "ch9",

					  "ch10", "ch11", "ch12", "ch13",

					  "ch14", "ch15";

			clocks = <&cpg CPG_MOD 709>;

			clock-names = "fck";

			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;

			resets = <&cpg 709>;

			#dma-cells = <1>;

			dma-channels = <16>;

		};



		dmac2: dma-controller@e7351000 {

			compatible = "renesas,dmac-r8a779a0";

			reg = <0 0xe7351000 0 0x1000>,

			      <0 0xe7310000 0 0x10000>;

			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "error",

					  "ch0", "ch1", "ch2", "ch3", "ch4",

					  "ch5", "ch6", "ch7";

			clocks = <&cpg CPG_MOD 710>;

			clock-names = "fck";

			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;

			resets = <&cpg 710>;

			#dma-cells = <1>;

			dma-channels = <8>;

		};



		gic: interrupt-controller@f1000000 {

			compatible = "arm,gic-v3";

			#interrupt-cells = <3>;