Commit 1f957fbb authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Biju Das
Browse files

drm: renesas: rz-du: Add support for RZ/V2H(P) SoC 



The LCD controller (LCDC) on the RZ/V2H(P) SoC is composed of Frame
Compression Processor (FCPVD), Video Signal Processor (VSPD), and
Display Unit (DU).

There is one LCDC unit available on the RZ/V2H(P) SoC which is connected
to the DSI.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250512182330.238259-3-prabhakar.mahadev-lad.rj@bp.renesas.com
parent ed6a6d63

drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c

+11 −0
Original line number Diff line number Diff line
@@ -50,9 +50,20 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = { 
	}

};



static const struct rzg2l_du_device_info rzg2l_du_r9a09g057_info = {

	.channels_mask = BIT(0),

	.routes = {

		[RZG2L_DU_OUTPUT_DSI0] = {

			.possible_outputs = BIT(0),

			.port = 0,

		},

	},

};



static const struct of_device_id rzg2l_du_of_table[] = {

	{ .compatible = "renesas,r9a07g043u-du", .data = &rzg2l_du_r9a07g043u_info },

	{ .compatible = "renesas,r9a07g044-du", .data = &rzg2l_du_r9a07g044_info },

	{ .compatible = "renesas,r9a09g057-du", .data = &rzg2l_du_r9a09g057_info },

	{ /* sentinel */ }

};