Commit 1fa5c5a3 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amd/display: add clear_tiling hubp callbacks 



This adds clear_tiling callbacks to the hubp structure that
will be used for drm panic support to clear the tiling on
a display.  hubp3 support from Jocelyn's original patch
and the rest from me.

Reviewed-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: Lu Yao <yaolu@kylinos.cn>
Cc: Jocelyn Falempe <jfalempe@redhat.com>
Cc: Harry Wentland <harry.wentland@amd.com>
parent fe151ed7

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

+15 −0
Original line number Diff line number Diff line
@@ -518,6 +518,20 @@ bool hubp1_program_surface_flip_and_addr( 
	return true;

}



void hubp1_clear_tiling(struct hubp *hubp)

{

	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);



	REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0);

	REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);



	REG_UPDATE_4(DCSURF_SURFACE_CONTROL,

		     PRIMARY_SURFACE_DCC_EN, 0,

		     PRIMARY_SURFACE_DCC_IND_64B_BLK, 0,

		     SECONDARY_SURFACE_DCC_EN, 0,

		     SECONDARY_SURFACE_DCC_IND_64B_BLK, 0);

}



void hubp1_dcc_control(struct hubp *hubp, bool enable,

		enum hubp_ind_block_size independent_64b_blks)

{
@@ -1363,6 +1377,7 @@ static const struct hubp_funcs dcn10_hubp_funcs = { 
	.hubp_disable_control =  hubp1_disable_control,

	.hubp_get_underflow_status = hubp1_get_underflow_status,

	.hubp_init = hubp1_init,

	.hubp_clear_tiling = hubp1_clear_tiling,



	.dmdata_set_attributes = NULL,

	.dmdata_load = NULL,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

+2 −0
Original line number Diff line number Diff line
@@ -794,4 +794,6 @@ void hubp1_soft_reset(struct hubp *hubp, bool reset); 


void hubp1_set_flip_int(struct hubp *hubp);



void hubp1_clear_tiling(struct hubp *hubp);



#endif

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

+15 −0
Original line number Diff line number Diff line
@@ -406,6 +406,20 @@ void hubp2_program_rotation( 
				H_MIRROR_EN, mirror);

}



void hubp2_clear_tiling(struct hubp *hubp)

{

	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);



	REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0);

	REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);



	REG_UPDATE_4(DCSURF_SURFACE_CONTROL,

		     PRIMARY_SURFACE_DCC_EN, 0,

		     PRIMARY_SURFACE_DCC_IND_64B_BLK, 0,

		     SECONDARY_SURFACE_DCC_EN, 0,

		     SECONDARY_SURFACE_DCC_IND_64B_BLK, 0);

}



void hubp2_dcc_control(struct hubp *hubp, bool enable,

		enum hubp_ind_block_size independent_64b_blks)

{
@@ -1676,6 +1690,7 @@ static struct hubp_funcs dcn20_hubp_funcs = { 
	.hubp_in_blank = hubp1_in_blank,

	.hubp_soft_reset = hubp1_soft_reset,

	.hubp_set_flip_int = hubp1_set_flip_int,

	.hubp_clear_tiling = hubp2_clear_tiling,

};

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h

+2 −0
Original line number Diff line number Diff line
@@ -409,6 +409,8 @@ void hubp2_read_state_common(struct hubp *hubp); 


void hubp2_read_state(struct hubp *hubp);



void hubp2_clear_tiling(struct hubp *hubp);



#endif /* __DC_MEM_INPUT_DCN20_H__ */

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

+1 −0
Original line number Diff line number Diff line
@@ -131,6 +131,7 @@ static struct hubp_funcs dcn201_hubp_funcs = { 
	.hubp_clear_underflow = hubp1_clear_underflow,

	.hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,

	.hubp_init = hubp1_init,

	.hubp_clear_tiling = hubp1_clear_tiling,

};



bool dcn201_hubp_construct(