Commit 1fbad9ac authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/irq: hide display_irqs_enabled access 



Move the check for display_irqs_enabled within vlv_display_irq_reset()
and vlv_display_irq_postinstall() to avoid looking at struct
intel_display members within i915 core irq code.

Within display irq code, vlv_display_irq_reset() may need to be called
with !display_irqs_enabled, so add a small wrapper.

Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ef43e26ebab7f84768391f5053c0eba44b647c89.1732102179.git.jani.nikula@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent d9b31d6a

drivers/gpu/drm/i915/display/intel_display_irq.c

+12 −3
Original line number Diff line number Diff line
@@ -1481,7 +1481,7 @@ void bdw_disable_vblank(struct drm_crtc *_crtc) 
		schedule_work(&display->irq.vblank_dc_work);

}



void vlv_display_irq_reset(struct drm_i915_private *dev_priv)

static void _vlv_display_irq_reset(struct drm_i915_private *dev_priv)

{

	struct intel_uncore *uncore = &dev_priv->uncore;
@@ -1499,6 +1499,12 @@ void vlv_display_irq_reset(struct drm_i915_private *dev_priv) 
	dev_priv->irq_mask = ~0u;

}



void vlv_display_irq_reset(struct drm_i915_private *dev_priv)

{

	if (dev_priv->display.irq.display_irqs_enabled)

		_vlv_display_irq_reset(dev_priv);

}



void i9xx_display_irq_reset(struct drm_i915_private *i915)

{

	if (I915_HAS_HOTPLUG(i915)) {
@@ -1518,6 +1524,9 @@ void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) 
	u32 enable_mask;

	enum pipe pipe;



	if (!dev_priv->display.irq.display_irqs_enabled)

		return;



	pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;



	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
@@ -1696,7 +1705,7 @@ void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) 
	dev_priv->display.irq.display_irqs_enabled = true;



	if (intel_irqs_enabled(dev_priv)) {

		vlv_display_irq_reset(dev_priv);

		_vlv_display_irq_reset(dev_priv);

		vlv_display_irq_postinstall(dev_priv);

	}

}
@@ -1711,7 +1720,7 @@ void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) 
	dev_priv->display.irq.display_irqs_enabled = false;



	if (intel_irqs_enabled(dev_priv))

		vlv_display_irq_reset(dev_priv);

		_vlv_display_irq_reset(dev_priv);

}



void ilk_de_irq_postinstall(struct drm_i915_private *i915)

drivers/gpu/drm/i915/i915_irq.c

+4 −8
Original line number Diff line number Diff line
@@ -658,7 +658,6 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv) 
	gen5_gt_irq_reset(to_gt(dev_priv));



	spin_lock_irq(&dev_priv->irq_lock);

	if (dev_priv->display.irq.display_irqs_enabled)

	vlv_display_irq_reset(dev_priv);

	spin_unlock_irq(&dev_priv->irq_lock);

}
@@ -723,7 +722,6 @@ static void cherryview_irq_reset(struct drm_i915_private *dev_priv) 
	gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS);



	spin_lock_irq(&dev_priv->irq_lock);

	if (dev_priv->display.irq.display_irqs_enabled)

	vlv_display_irq_reset(dev_priv);

	spin_unlock_irq(&dev_priv->irq_lock);

}
@@ -740,7 +738,6 @@ static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv) 
	gen5_gt_irq_postinstall(to_gt(dev_priv));



	spin_lock_irq(&dev_priv->irq_lock);

	if (dev_priv->display.irq.display_irqs_enabled)

	vlv_display_irq_postinstall(dev_priv);

	spin_unlock_irq(&dev_priv->irq_lock);
@@ -794,7 +791,6 @@ static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv) 
	gen8_gt_irq_postinstall(to_gt(dev_priv));



	spin_lock_irq(&dev_priv->irq_lock);

	if (dev_priv->display.irq.display_irqs_enabled)

	vlv_display_irq_postinstall(dev_priv);

	spin_unlock_irq(&dev_priv->irq_lock);