Unverified Commit 1fcf4149 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'riscv-dt-fixes-for-v7.1-rc3' of... 

Merge tag 'riscv-dt-fixes-for-v7.1-rc3' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux

 into arm/fixes

RISC-V devicetrees fixes for v7.1-rc3

Microchip:
Fix a pinctrl misconfiguration caused by a erratum fixed between
engineering sample and production silicon, that causes settings for one
to not apply to the other.

Starfive:
Remove nodes relating to the "camss" video device that has been deleted
entirely from staging.

Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>

* tag 'riscv-dt-fixes-for-v7.1-rc3' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux

:
  riscv: dts: microchip: fix icicle i2c pinctrl configuration
  riscv: dts: starfive: jh7110: Drop CAMSS node

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 7602c0ec 0df8aa2b

arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi

+0 −10
Original line number Diff line number Diff line
@@ -101,16 +101,6 @@ &ccc_nw { 
	status = "okay";

};



&i2c0 {

	pinctrl-names = "default";

	pinctrl-0 = <&i2c0_fabric>;

};



&i2c1 {

	pinctrl-names = "default";

	pinctrl-0 = <&i2c1_mssio>;

};



&mmuart1 {

	pinctrl-names = "default";

	pinctrl-0 = <&uart1_fabric>;

arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts

+10 −0
Original line number Diff line number Diff line
@@ -14,6 +14,16 @@ / { 
		     "microchip,mpfs";

};



&i2c0 {

	pinctrl-names = "default";

	pinctrl-0 = <&i2c0_fabric>;

};



&i2c1 {

	pinctrl-names = "default";

	pinctrl-0 = <&i2c1_mssio>;

};



&syscontroller {

	microchip,bitstream-flash = <&sys_ctrl_flash>;

};

arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts

+19 −0
Original line number Diff line number Diff line
@@ -11,3 +11,22 @@ / { 
		     "microchip,mpfs-icicle-kit",

		     "microchip,mpfs";

};



&i2c0 {

	pinctrl-names = "default";

	pinctrl-0 = <&i2c0_fabric>;

};



/*

 * Due to silicon errata, routing via MSS IOs doesn't work on ES devices.

 * Instead, i2c1, appearing on B1/C1, which are normally MSS IOs, is routed

 * via the fabric and back to B1/C1 via "fabric-test" functionality.

 * This is done silently by Libero, so the iomux0 setting for i2c1 has to

 * be fabric IO, despite tooling etc saying that MSS IOs are used.

 *

 * See Section 3.3 of https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/Errata/polarfiresoc/microsemi_polarfire_soc_fpga_egineering_samples_errata_er0219_v1.pdf

 */

&i2c1 {

	pinctrl-names = "default";

	pinctrl-0 = <&i2c1_fabric>;

};

arch/riscv/boot/dts/starfive/jh7110-common.dtsi

+1 −26
Original line number Diff line number Diff line
@@ -135,29 +135,6 @@ &tdm_ext { 
	clock-frequency = <49152000>;

};



&camss {

	assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,

			  <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>;

	assigned-clock-rates = <49500000>, <198000000>;



	ports {

		#address-cells = <1>;

		#size-cells = <0>;



		port@0 {

			reg = <0>;

		};



		port@1 {

			reg = <1>;



			camss_from_csi2rx: endpoint {

				remote-endpoint = <&csi2rx_to_camss>;

			};

		};

	};

};



&csi2rx {

	assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>;

	assigned-clock-rates = <297000000>;
@@ -175,9 +152,7 @@ port@0 { 
		port@1 {

			reg = <1>;



			csi2rx_to_camss: endpoint {

				remote-endpoint = <&camss_from_csi2rx>;

			};

			/* remote CAMSS endpoint */

		};

	};

};

arch/riscv/boot/dts/starfive/jh7110.dtsi

+0 −28
Original line number Diff line number Diff line
@@ -1199,34 +1199,6 @@ csi_phy: phy@19820000 { 
			#phy-cells = <0>;

		};



		camss: isp@19840000 {

			compatible = "starfive,jh7110-camss";

			reg = <0x0 0x19840000 0x0 0x10000>,

			      <0x0 0x19870000 0x0 0x30000>;

			reg-names = "syscon", "isp";

			clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,

				 <&ispcrg JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C>,

				 <&ispcrg JH7110_ISPCLK_DVP_INV>,

				 <&ispcrg JH7110_ISPCLK_VIN_P_AXI_WR>,

				 <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>,

				 <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,

				 <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>;

			clock-names = "apb_func", "wrapper_clk_c", "dvp_inv",

				      "axiwr", "mipi_rx0_pxl", "ispcore_2x",

				      "isp_axi";

			resets = <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_P>,

				 <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_C>,

				 <&ispcrg JH7110_ISPRST_VIN_P_AXI_RD>,

				 <&ispcrg JH7110_ISPRST_VIN_P_AXI_WR>,

				 <&syscrg JH7110_SYSRST_ISP_TOP>,

				 <&syscrg JH7110_SYSRST_ISP_TOP_AXI>;

			reset-names = "wrapper_p", "wrapper_c", "axird",

				      "axiwr", "isp_top_n", "isp_top_axi";

			power-domains = <&pwrc JH7110_PD_ISP>;

			interrupts = <92>, <87>, <90>, <88>;

			status = "disabled";

		};



		voutcrg: clock-controller@295c0000 {

			compatible = "starfive,jh7110-voutcrg";

			reg = <0x0 0x295c0000 0x0 0x10000>;