Commit 1fd7c37e authored by YuanShang's avatar YuanShang Committed by Alex Deucher
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drm/amdgpu: Flush tlb by VM_INVALIDATION packet in sdma_v5_2 



In order for SDMA not to be switched between VM_INVALIDATION
request and ack, use an single VM_INVALIDATION packet in function
sdma_v5_2_ring_emit_vm_flush.

Signed-off-by: default avatarYuanShang <YuanShang.Mao@amd.com>
Reviewed-By: default avatarHorace Chen <horace.chen@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 64acf8f6

drivers/gpu/drm/amd/amdgpu/navi10_sdma_pkt_open.h

+64 −0
Original line number Diff line number Diff line
@@ -68,6 +68,7 @@ 
#define SDMA_SUBOP_POLL_REG_WRITE_MEM  1

#define SDMA_SUBOP_POLL_DBIT_WRITE_MEM  2

#define SDMA_SUBOP_POLL_MEM_VERIFY  3

#define SDMA_SUBOP_VM_INVALIDATION  4

#define HEADER_AGENT_DISPATCH  4

#define HEADER_BARRIER  5

#define SDMA_OP_AQL_COPY  0
@@ -4040,6 +4041,69 @@ 
#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask) << SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift)





/*

** Definitions for SDMA_PKT_VM_INVALIDATION packet

*/



/*define for HEADER word*/

/*define for op field*/

#define SDMA_PKT_VM_INVALIDATION_HEADER_op_offset 0

#define SDMA_PKT_VM_INVALIDATION_HEADER_op_mask   0x000000FF

#define SDMA_PKT_VM_INVALIDATION_HEADER_op_shift  0

#define SDMA_PKT_VM_INVALIDATION_HEADER_OP(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_op_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_op_shift)



/*define for sub_op field*/

#define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset 0

#define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask   0x000000FF

#define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift  8

#define SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift)



/*define for gfx_eng_id field*/

#define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_offset 0

#define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask   0x0000001F

#define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift  16

#define SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift)



/*define for mm_eng_id field*/

#define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_offset 0

#define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask   0x0000001F

#define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift  24

#define SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift)



/*define for INVALIDATEREQ word*/

/*define for invalidatereq field*/

#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset 1

#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask   0xFFFFFFFF

#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift  0

#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_INVALIDATEREQ(x) (((x) & SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask) << SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift)



/*define for ADDRESSRANGELO word*/

/*define for addressrangelo field*/

#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset 2

#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask   0xFFFFFFFF

#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift  0

#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_ADDRESSRANGELO(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift)



/*define for ADDRESSRANGEHI word*/

/*define for invalidateack field*/

#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset 3

#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask   0x0000FFFF

#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift  0

#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift)



/*define for addressrangehi field*/

#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset 3

#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask   0x0000001F

#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift  16

#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift)



/*define for reserved field*/

#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset 3

#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask   0x000001FF

#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift  23

#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_RESERVED(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift)





/*

** Definitions for SDMA_PKT_ATOMIC packet

*/

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

+22 −1
Original line number Diff line number Diff line
@@ -1205,7 +1205,28 @@ static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 
static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,

					 unsigned vmid, uint64_t pd_addr)

{

	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);

	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];

	uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);



	/* Update the PD address for this VMID. */

	amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +

			      (hub->ctx_addr_distance * vmid),

			      lower_32_bits(pd_addr));

	amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +

			      (hub->ctx_addr_distance * vmid),

			      upper_32_bits(pd_addr));



	/* Trigger invalidation. */

	amdgpu_ring_write(ring,

			  SDMA_PKT_VM_INVALIDATION_HEADER_OP(SDMA_OP_POLL_REGMEM) |

			  SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(SDMA_SUBOP_VM_INVALIDATION) |

			  SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(ring->vm_inv_eng) |

			  SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(0x1f));

	amdgpu_ring_write(ring, req);

	amdgpu_ring_write(ring, 0xFFFFFFFF);

	amdgpu_ring_write(ring,

			  SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(1 << vmid) |

			  SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(0x1F));

}



static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,